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[PULL 18/54] target/riscv: use isa_ext_update_enabled() in init_max_cpu_
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From: |
Alistair Francis |
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Subject: |
[PULL 18/54] target/riscv: use isa_ext_update_enabled() in init_max_cpu_extensions() |
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Date: |
Thu, 12 Oct 2023 14:10:15 +1000 |
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Before adding support to detect if an extension was user set we need to
handle how we're enabling extensions in riscv_init_max_cpu_extensions().
object_property_set_bool() calls the set() callback for the property,
and we're going to use this callback to set the 'multi_ext_user_opts'
hash.
This means that, as is today, all extensions we're setting for the 'max'
CPU will be seen as user set in the future. Let's change set_bool() to
isa_ext_update_enabled() that will just enable/disable the flag on a
certain offset.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20230912132423.268494-19-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index fba5ce7118..821006f42a 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -2166,24 +2166,24 @@ static void riscv_init_max_cpu_extensions(Object *obj)
set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV);
for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
- object_property_set_bool(obj, prop->name, true, NULL);
+ isa_ext_update_enabled(cpu, prop->offset, true);
}
/* set vector version */
env->vext_ver = VEXT_VERSION_1_00_0;
/* Zfinx is not compatible with F. Disable it */
- object_property_set_bool(obj, "zfinx", false, NULL);
- object_property_set_bool(obj, "zdinx", false, NULL);
- object_property_set_bool(obj, "zhinx", false, NULL);
- object_property_set_bool(obj, "zhinxmin", false, NULL);
+ isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zfinx), false);
+ isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zdinx), false);
+ isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinx), false);
+ isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinxmin), false);
- object_property_set_bool(obj, "zce", false, NULL);
- object_property_set_bool(obj, "zcmp", false, NULL);
- object_property_set_bool(obj, "zcmt", false, NULL);
+ isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zce), false);
+ isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmp), false);
+ isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmt), false);
if (env->misa_mxl != MXL_RV32) {
- object_property_set_bool(obj, "zcf", false, NULL);
+ isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcf), false);
}
}
--
2.41.0
- [PULL 11/54] avocado, risc-v: add tuxboot tests for 'max' CPU, (continued)
- [PULL 11/54] avocado, risc-v: add tuxboot tests for 'max' CPU, Alistair Francis, 2023/10/12
- [PULL 10/54] target/riscv: add 'max' CPU type, Alistair Francis, 2023/10/12
- [PULL 12/54] target/riscv: deprecate the 'any' CPU type, Alistair Francis, 2023/10/12
- [PULL 13/54] target/riscv/cpu.c: use offset in isa_ext_is_enabled/update_enabled, Alistair Francis, 2023/10/12
- [PULL 14/54] target/riscv: make CPUCFG() macro public, Alistair Francis, 2023/10/12
- [PULL 06/54] target/riscv/cpu.c: split vendor exts from riscv_cpu_extensions[], Alistair Francis, 2023/10/12
- [PULL 09/54] target/riscv/cpu.c: limit cfg->vext_spec log message, Alistair Francis, 2023/10/12
- [PULL 16/54] target/riscv/cpu.c: use cpu_cfg_ext_auto_update() during realize(), Alistair Francis, 2023/10/12
- [PULL 15/54] target/riscv/cpu.c: introduce cpu_cfg_ext_auto_update(), Alistair Francis, 2023/10/12
- [PULL 17/54] target/riscv/cpu.c: introduce RISCVCPUMultiExtConfig, Alistair Francis, 2023/10/12
- [PULL 18/54] target/riscv: use isa_ext_update_enabled() in init_max_cpu_extensions(),
Alistair Francis <=
- [PULL 19/54] target/riscv/cpu.c: honor user choice in cpu_cfg_ext_auto_update(), Alistair Francis, 2023/10/12
- [PULL 20/54] target/riscv/cpu.c: consider user option with RVG, Alistair Francis, 2023/10/12
- [PULL 21/54] target/riscv: Clear CSR values at reset and sync MPSTATE with host, Alistair Francis, 2023/10/12
- [PULL 22/54] disas/riscv: Fix the typo of inverted order of pmpaddr13 and pmpaddr14, Alistair Francis, 2023/10/12
- [PULL 23/54] target/riscv: introduce TCG AccelCPUClass, Alistair Francis, 2023/10/12
- [PULL 24/54] target/riscv: move riscv_cpu_realize_tcg() to TCG::cpu_realizefn(), Alistair Francis, 2023/10/12
- [PULL 26/54] target/riscv: move riscv_tcg_ops to tcg-cpu.c, Alistair Francis, 2023/10/12
- [PULL 25/54] target/riscv: move riscv_cpu_validate_set_extensions() to tcg-cpu.c, Alistair Francis, 2023/10/12
- [PULL 27/54] target/riscv/cpu.c: add .instance_post_init(), Alistair Francis, 2023/10/12
- [PULL 28/54] target/riscv: move 'host' CPU declaration to kvm.c, Alistair Francis, 2023/10/12