[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 33/54] target/riscv: introduce KVM AccelCPUClass
|
From: |
Alistair Francis |
|
Subject: |
[PULL 33/54] target/riscv: introduce KVM AccelCPUClass |
|
Date: |
Thu, 12 Oct 2023 14:10:30 +1000 |
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Add a KVM accelerator class like we did with TCG. The difference is
that, at least for now, we won't be using a realize() implementation for
this accelerator.
We'll start by assiging kvm_riscv_cpu_add_kvm_properties(), renamed to
kvm_cpu_instance_init(), as a 'cpu_instance_init' implementation. Change
riscv_cpu_post_init() to invoke accel_cpu_instance_init(), which will go
through the 'cpu_instance_init' impl of the current acceleration (if
available) and execute it. The end result is that the KVM initial setup,
i.e. starting registers and adding its specific properties, will be done
via this hook.
Add a 'tcg_enabled()' condition in riscv_cpu_post_init() to avoid
calling riscv_cpu_add_user_properties() when running KVM. We'll remove
this condition when the TCG accel class get its own 'cpu_instance_init'
implementation.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20230925175709.35696-12-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/kvm_riscv.h | 1 -
target/riscv/cpu.c | 8 +++-----
target/riscv/kvm.c | 26 ++++++++++++++++++++++++--
3 files changed, 27 insertions(+), 8 deletions(-)
diff --git a/target/riscv/kvm_riscv.h b/target/riscv/kvm_riscv.h
index da9630c4af..8329cfab82 100644
--- a/target/riscv/kvm_riscv.h
+++ b/target/riscv/kvm_riscv.h
@@ -19,7 +19,6 @@
#ifndef QEMU_KVM_RISCV_H
#define QEMU_KVM_RISCV_H
-void kvm_riscv_cpu_add_kvm_properties(Object *obj);
void kvm_riscv_reset_vcpu(RISCVCPU *cpu);
void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level);
void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift,
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 143fbc1fbc..648b9f7af7 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1219,7 +1219,9 @@ static bool riscv_cpu_has_user_properties(Object *cpu_obj)
static void riscv_cpu_post_init(Object *obj)
{
- if (riscv_cpu_has_user_properties(obj)) {
+ accel_cpu_instance_init(CPU(obj));
+
+ if (tcg_enabled() && riscv_cpu_has_user_properties(obj)) {
riscv_cpu_add_user_properties(obj);
}
@@ -1585,10 +1587,6 @@ static void riscv_cpu_add_multiext_prop_array(Object
*obj,
static void riscv_cpu_add_user_properties(Object *obj)
{
#ifndef CONFIG_USER_ONLY
- if (kvm_enabled()) {
- kvm_riscv_cpu_add_kvm_properties(obj);
- return;
- }
riscv_add_satp_mode_properties(obj);
#endif
diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
index e5e957121f..606fdab223 100644
--- a/target/riscv/kvm.c
+++ b/target/riscv/kvm.c
@@ -31,6 +31,7 @@
#include "sysemu/kvm_int.h"
#include "cpu.h"
#include "trace.h"
+#include "hw/core/accel-cpu.h"
#include "hw/pci/pci.h"
#include "exec/memattrs.h"
#include "exec/address-spaces.h"
@@ -1318,8 +1319,9 @@ void kvm_riscv_aia_create(MachineState *machine, uint64_t
group_shift,
kvm_msi_via_irqfd_allowed = kvm_irqfds_enabled();
}
-void kvm_riscv_cpu_add_kvm_properties(Object *obj)
+static void kvm_cpu_instance_init(CPUState *cs)
{
+ Object *obj = OBJECT(RISCV_CPU(cs));
DeviceState *dev = DEVICE(obj);
riscv_init_user_properties(obj);
@@ -1331,7 +1333,7 @@ void kvm_riscv_cpu_add_kvm_properties(Object *obj)
riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_experimental_exts);
for (Property *prop = riscv_cpu_options; prop && prop->name; prop++) {
- /* Check if KVM created the property already */
+ /* Check if we have a specific KVM handler for the option */
if (object_property_find(obj, prop->name)) {
continue;
}
@@ -1339,6 +1341,26 @@ void kvm_riscv_cpu_add_kvm_properties(Object *obj)
}
}
+static void kvm_cpu_accel_class_init(ObjectClass *oc, void *data)
+{
+ AccelCPUClass *acc = ACCEL_CPU_CLASS(oc);
+
+ acc->cpu_instance_init = kvm_cpu_instance_init;
+}
+
+static const TypeInfo kvm_cpu_accel_type_info = {
+ .name = ACCEL_CPU_NAME("kvm"),
+
+ .parent = TYPE_ACCEL_CPU,
+ .class_init = kvm_cpu_accel_class_init,
+ .abstract = true,
+};
+static void kvm_cpu_accel_register_types(void)
+{
+ type_register_static(&kvm_cpu_accel_type_info);
+}
+type_init(kvm_cpu_accel_register_types);
+
static void riscv_host_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
--
2.41.0
- [PULL 23/54] target/riscv: introduce TCG AccelCPUClass, (continued)
- [PULL 23/54] target/riscv: introduce TCG AccelCPUClass, Alistair Francis, 2023/10/12
- [PULL 24/54] target/riscv: move riscv_cpu_realize_tcg() to TCG::cpu_realizefn(), Alistair Francis, 2023/10/12
- [PULL 26/54] target/riscv: move riscv_tcg_ops to tcg-cpu.c, Alistair Francis, 2023/10/12
- [PULL 25/54] target/riscv: move riscv_cpu_validate_set_extensions() to tcg-cpu.c, Alistair Francis, 2023/10/12
- [PULL 27/54] target/riscv/cpu.c: add .instance_post_init(), Alistair Francis, 2023/10/12
- [PULL 28/54] target/riscv: move 'host' CPU declaration to kvm.c, Alistair Francis, 2023/10/12
- [PULL 29/54] target/riscv/cpu.c: mark extensions arrays as 'const', Alistair Francis, 2023/10/12
- [PULL 30/54] target/riscv: move riscv_cpu_add_kvm_properties() to kvm.c, Alistair Francis, 2023/10/12
- [PULL 31/54] target/riscv: make riscv_add_satp_mode_properties() public, Alistair Francis, 2023/10/12
- [PULL 32/54] target/riscv: remove kvm-stub.c, Alistair Francis, 2023/10/12
- [PULL 33/54] target/riscv: introduce KVM AccelCPUClass,
Alistair Francis <=
- [PULL 34/54] target/riscv: move KVM only files to kvm subdir, Alistair Francis, 2023/10/12
- [PULL 35/54] target/riscv/kvm: do not use riscv_cpu_add_misa_properties(), Alistair Francis, 2023/10/12
- [PULL 36/54] target/riscv/cpu.c: export set_misa(), Alistair Francis, 2023/10/12
- [PULL 37/54] target/riscv/tcg: introduce tcg_cpu_instance_init(), Alistair Francis, 2023/10/12
- [PULL 38/54] target/riscv/cpu.c: make misa_ext_cfgs[] 'const', Alistair Francis, 2023/10/12
- [PULL 39/54] target/riscv/tcg: move riscv_cpu_add_misa_properties() to tcg-cpu.c, Alistair Francis, 2023/10/12
- [PULL 40/54] target/riscv/cpu.c: export isa_edata_arr[], Alistair Francis, 2023/10/12
- [PULL 41/54] target/riscv/cpu: move priv spec functions to tcg-cpu.c, Alistair Francis, 2023/10/12
- [PULL 42/54] target/riscv: add riscv_cpu_get_name(), Alistair Francis, 2023/10/12
- [PULL 43/54] target/riscv/tcg-cpu.c: add extension properties for all cpus, Alistair Francis, 2023/10/12