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[PATCH 25/61] target/hppa: Pass d to do_sed_cond
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From: |
Richard Henderson |
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Subject: |
[PATCH 25/61] target/hppa: Pass d to do_sed_cond |
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Date: |
Wed, 18 Oct 2023 14:50:59 -0700 |
Hoist the resolution of d up one level above do_sed_cond.
The MOVB comparison and the existing shift/extract/deposit
are all 32-bit.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/translate.c | 24 +++++++++++++-----------
1 file changed, 13 insertions(+), 11 deletions(-)
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 7a3b0f1de7..1a51ac4869 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -1037,10 +1037,10 @@ static DisasCond do_log_cond(DisasContext *ctx,
unsigned cf, bool d,
/* Similar, but for shift/extract/deposit conditions. */
-static DisasCond do_sed_cond(DisasContext *ctx, unsigned orig, TCGv_reg res)
+static DisasCond do_sed_cond(DisasContext *ctx, unsigned orig, bool d,
+ TCGv_reg res)
{
unsigned c, f;
- bool d = false;
/* Convert the compressed condition codes to standard.
0-2 are the same as logicals (nv,<,<=), while 3 is OD.
@@ -3203,7 +3203,8 @@ static bool trans_movb(DisasContext *ctx, arg_movb *a)
tcg_gen_mov_reg(dest, cpu_gr[a->r1]);
}
- cond = do_sed_cond(ctx, a->c, dest);
+ /* All MOVB conditions are 32-bit. */
+ cond = do_sed_cond(ctx, a->c, false, dest);
return do_cbranch(ctx, a->disp, a->n, &cond);
}
@@ -3217,7 +3218,8 @@ static bool trans_movbi(DisasContext *ctx, arg_movbi *a)
dest = dest_gpr(ctx, a->r);
tcg_gen_movi_reg(dest, a->i);
- cond = do_sed_cond(ctx, a->c, dest);
+ /* All MOVBI conditions are 32-bit. */
+ cond = do_sed_cond(ctx, a->c, false, dest);
return do_cbranch(ctx, a->disp, a->n, &cond);
}
@@ -3255,7 +3257,7 @@ static bool trans_shrpw_sar(DisasContext *ctx,
arg_shrpw_sar *a)
/* Install the new nullification. */
cond_free(&ctx->null_cond);
if (a->c) {
- ctx->null_cond = do_sed_cond(ctx, a->c, dest);
+ ctx->null_cond = do_sed_cond(ctx, a->c, false, dest);
}
return nullify_end(ctx);
}
@@ -3291,7 +3293,7 @@ static bool trans_shrpw_imm(DisasContext *ctx,
arg_shrpw_imm *a)
/* Install the new nullification. */
cond_free(&ctx->null_cond);
if (a->c) {
- ctx->null_cond = do_sed_cond(ctx, a->c, dest);
+ ctx->null_cond = do_sed_cond(ctx, a->c, false, dest);
}
return nullify_end(ctx);
}
@@ -3325,7 +3327,7 @@ static bool trans_extrw_sar(DisasContext *ctx,
arg_extrw_sar *a)
/* Install the new nullification. */
cond_free(&ctx->null_cond);
if (a->c) {
- ctx->null_cond = do_sed_cond(ctx, a->c, dest);
+ ctx->null_cond = do_sed_cond(ctx, a->c, false, dest);
}
return nullify_end(ctx);
}
@@ -3352,7 +3354,7 @@ static bool trans_extrw_imm(DisasContext *ctx,
arg_extrw_imm *a)
/* Install the new nullification. */
cond_free(&ctx->null_cond);
if (a->c) {
- ctx->null_cond = do_sed_cond(ctx, a->c, dest);
+ ctx->null_cond = do_sed_cond(ctx, a->c, false, dest);
}
return nullify_end(ctx);
}
@@ -3389,7 +3391,7 @@ static bool trans_depwi_imm(DisasContext *ctx,
arg_depwi_imm *a)
/* Install the new nullification. */
cond_free(&ctx->null_cond);
if (a->c) {
- ctx->null_cond = do_sed_cond(ctx, a->c, dest);
+ ctx->null_cond = do_sed_cond(ctx, a->c, false, dest);
}
return nullify_end(ctx);
}
@@ -3419,7 +3421,7 @@ static bool trans_depw_imm(DisasContext *ctx,
arg_depw_imm *a)
/* Install the new nullification. */
cond_free(&ctx->null_cond);
if (a->c) {
- ctx->null_cond = do_sed_cond(ctx, a->c, dest);
+ ctx->null_cond = do_sed_cond(ctx, a->c, false, dest);
}
return nullify_end(ctx);
}
@@ -3456,7 +3458,7 @@ static bool do_depw_sar(DisasContext *ctx, unsigned rt,
unsigned c,
/* Install the new nullification. */
cond_free(&ctx->null_cond);
if (c) {
- ctx->null_cond = do_sed_cond(ctx, c, dest);
+ ctx->null_cond = do_sed_cond(ctx, c, false, dest);
}
return nullify_end(ctx);
}
--
2.34.1
- [PATCH 11/61] target/hppa: Fix extrw and depw with sar for hppa64, (continued)
- [PATCH 11/61] target/hppa: Fix extrw and depw with sar for hppa64, Richard Henderson, 2023/10/18
- [PATCH 14/61] target/hppa: Implement cpu_list, Richard Henderson, 2023/10/18
- [PATCH 17/61] target/hppa: Handle absolute addresses for pa2.0, Richard Henderson, 2023/10/18
- [PATCH 30/61] target/hppa: Decode d for logical instructions, Richard Henderson, 2023/10/18
- [PATCH 27/61] linux-user/hppa: Fixes for TARGET_ABI32, Richard Henderson, 2023/10/18
- [PATCH 36/61] target/hppa: Decode d for cmpb instructions, Richard Henderson, 2023/10/18
- [PATCH 38/61] target/hppa: Decode ADDB double-word, Richard Henderson, 2023/10/18
- [PATCH 19/61] hw/hppa: Translate phys addresses for the cpu, Richard Henderson, 2023/10/18
- [PATCH 04/61] target/hppa: Remove load_const, Richard Henderson, 2023/10/18
- [PATCH 20/61] target/hppa: Fix hppa64 addressing, Richard Henderson, 2023/10/18
- [PATCH 25/61] target/hppa: Pass d to do_sed_cond,
Richard Henderson <=
- [PATCH 29/61] target/hppa: Remove TARGET_HPPA64, Richard Henderson, 2023/10/18
- [PATCH 34/61] target/hppa: Decode d for sub instructions, Richard Henderson, 2023/10/18
- [PATCH 37/61] target/hppa: Decode CMPIB double-word, Richard Henderson, 2023/10/18
- [PATCH 15/61] target/hppa: Implement hppa_cpu_class_by_name, Richard Henderson, 2023/10/18
- [PATCH 16/61] target/hppa: Update cpu_hppa_get/put_psw for hppa64, Richard Henderson, 2023/10/18
- [PATCH 22/61] target/hppa: Pass d to do_cond, Richard Henderson, 2023/10/18
- [PATCH 23/61] target/hppa: Pass d to do_sub_cond, Richard Henderson, 2023/10/18
- [PATCH 24/61] target/hppa: Pass d to do_log_cond, Richard Henderson, 2023/10/18
- [PATCH 10/61] target/hppa: Fix bb_sar for hppa64, Richard Henderson, 2023/10/18
- [PATCH 21/61] target/hppa: sar register allows only 5 bits on 32-bit CPU, Richard Henderson, 2023/10/18