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[PATCH 50/61] target/hppa: Replace tcg_gen_*_tl with tcg_gen_*_i64
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From: |
Richard Henderson |
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Subject: |
[PATCH 50/61] target/hppa: Replace tcg_gen_*_tl with tcg_gen_*_i64 |
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Date: |
Wed, 18 Oct 2023 14:51:24 -0700 |
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/translate.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 4a2bfb7757..366a8f1acc 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -1325,10 +1325,10 @@ static void form_gva(DisasContext *ctx, TCGv_i64 *pgva,
TCGv_i64 *pofs,
*pofs = ofs;
*pgva = addr = tcg_temp_new_i64();
- tcg_gen_andi_tl(addr, modify <= 0 ? ofs : base, gva_offset_mask(ctx));
+ tcg_gen_andi_i64(addr, modify <= 0 ? ofs : base, gva_offset_mask(ctx));
#ifndef CONFIG_USER_ONLY
if (!is_phys) {
- tcg_gen_or_tl(addr, addr, space_select(ctx, sp, base));
+ tcg_gen_or_i64(addr, addr, space_select(ctx, sp, base));
}
#endif
}
@@ -2361,7 +2361,7 @@ static bool trans_ixtlbxf(DisasContext *ctx, arg_ixtlbxf
*a)
a->data ? offsetof(CPUHPPAState, cr[CR_IOR])
: offsetof(CPUHPPAState, cr[CR_IIAOQ]));
tcg_gen_shli_i64(stl, stl, 32);
- tcg_gen_or_tl(addr, atl, stl);
+ tcg_gen_or_i64(addr, atl, stl);
reg = load_gpr(ctx, a->r);
if (a->addr) {
@@ -2911,7 +2911,7 @@ static bool trans_ldo(DisasContext *ctx, arg_ldo *a)
TCGv_i64 tcg_rt = dest_gpr(ctx, a->t);
/* Special case rb == 0, for the LDI pseudo-op.
- The COPY pseudo-op is handled for free within tcg_gen_addi_tl. */
+ The COPY pseudo-op is handled for free within tcg_gen_addi_i64. */
if (a->b == 0) {
tcg_gen_movi_i64(tcg_rt, a->i);
} else {
--
2.34.1
- [PATCH 35/61] target/hppa: Decode d for bb instructions, (continued)
- [PATCH 35/61] target/hppa: Decode d for bb instructions, Richard Henderson, 2023/10/18
- [PATCH 39/61] target/hppa: Implement LDD, LDCD, LDDA, STD, STDA, Richard Henderson, 2023/10/18
- [PATCH 40/61] target/hppa: Implement DEPD, DEPDI, Richard Henderson, 2023/10/18
- [PATCH 41/61] target/hppa: Implement EXTRD, Richard Henderson, 2023/10/18
- [PATCH 44/61] target/hppa: Implement STDBY, Richard Henderson, 2023/10/18
- [PATCH 43/61] target/hppa: Implement CLRBTS, POPBTS, PUSHBTS, PUSHNOM, Richard Henderson, 2023/10/18
- [PATCH 45/61] target/hppa: Implement IDTLBT, IITLBT, Richard Henderson, 2023/10/18
- [PATCH 42/61] target/hppa: Implement SHRPD, Richard Henderson, 2023/10/18
- [PATCH 46/61] target/hppa: Remove TARGET_REGISTER_BITS, Richard Henderson, 2023/10/18
- [PATCH 47/61] target/hppa: Remove most of the TARGET_REGISTER_BITS redirections, Richard Henderson, 2023/10/18
- [PATCH 50/61] target/hppa: Replace tcg_gen_*_tl with tcg_gen_*_i64,
Richard Henderson <=
- [PATCH 52/61] target/hppa: Implement HSUB, Richard Henderson, 2023/10/18
- [PATCH 48/61] target/hppa: Remove remaining TARGET_REGISTER_BITS redirections, Richard Henderson, 2023/10/18
- [PATCH 49/61] target/hppa: Use tcg_temp_new_i64 not tcg_temp_new, Richard Henderson, 2023/10/18
- [PATCH 51/61] target/hppa: Implement HADD, Richard Henderson, 2023/10/18
- [PATCH 53/61] target/hppa: Implement HAVG, Richard Henderson, 2023/10/18
- [PATCH 54/61] target/hppa: Implement HSHL, HSHR, Richard Henderson, 2023/10/18
- [PATCH 56/61] target/hppa: Implement MIXH, MIXW, Richard Henderson, 2023/10/18
- [PATCH 55/61] target/hppa: Implement HSHLADD, HSHRADD, Richard Henderson, 2023/10/18
- [PATCH 58/61] target/hppa: Fix interruption based on default PSW, Richard Henderson, 2023/10/18
- [PATCH 59/61] target/hppa: Precompute zero into DisasContext, Richard Henderson, 2023/10/18