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[PATCH 57/61] target/hppa: Implement PERMH
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From: |
Richard Henderson |
|
Subject: |
[PATCH 57/61] target/hppa: Implement PERMH |
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Date: |
Wed, 18 Oct 2023 14:51:31 -0700 |
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/insns.decode | 2 ++
target/hppa/translate.c | 29 +++++++++++++++++++++++++++++
2 files changed, 31 insertions(+)
diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode
index 323e9275bf..c8f4317576 100644
--- a/target/hppa/insns.decode
+++ b/target/hppa/insns.decode
@@ -238,6 +238,8 @@ mixh_r 111110 ..... ..... 1 10 00100000 ..... @rrr
mixw_l 111110 ..... ..... 1 00 00000000 ..... @rrr
mixw_r 111110 ..... ..... 1 10 00000000 ..... @rrr
+permh 111110 r1:5 r2:5 0 c0:2 0 c1:2 c2:2 c3:2 0 t:5
+
####
# Index Mem
####
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index bd8a858da6..40b5a3d8c3 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -2918,6 +2918,35 @@ static bool trans_mixw_r(DisasContext *ctx, arg_rrr *a)
return do_multimedia(ctx, a, gen_mixw_r);
}
+static bool trans_permh(DisasContext *ctx, arg_permh *a)
+{
+ TCGv_i64 r, t0, t1, t2, t3;
+
+ if (!ctx->is_pa20) {
+ return false;
+ }
+
+ nullify_over(ctx);
+
+ r = load_gpr(ctx, a->r1);
+ t0 = tcg_temp_new_i64();
+ t1 = tcg_temp_new_i64();
+ t2 = tcg_temp_new_i64();
+ t3 = tcg_temp_new_i64();
+
+ tcg_gen_extract_i64(t0, r, (3 - a->c0) * 16, 16);
+ tcg_gen_extract_i64(t1, r, (3 - a->c1) * 16, 16);
+ tcg_gen_extract_i64(t2, r, (3 - a->c2) * 16, 16);
+ tcg_gen_extract_i64(t3, r, (3 - a->c3) * 16, 16);
+
+ tcg_gen_deposit_i64(t0, t1, t0, 16, 48);
+ tcg_gen_deposit_i64(t2, t3, t2, 16, 48);
+ tcg_gen_deposit_i64(t0, t2, t0, 32, 32);
+
+ save_gpr(ctx, a->t, t0);
+ return nullify_end(ctx);
+}
+
static bool trans_ld(DisasContext *ctx, arg_ldst *a)
{
if (!ctx->is_pa20 && a->size > MO_32) {
--
2.34.1
- [PATCH 52/61] target/hppa: Implement HSUB, (continued)
- [PATCH 52/61] target/hppa: Implement HSUB, Richard Henderson, 2023/10/18
- [PATCH 48/61] target/hppa: Remove remaining TARGET_REGISTER_BITS redirections, Richard Henderson, 2023/10/18
- [PATCH 49/61] target/hppa: Use tcg_temp_new_i64 not tcg_temp_new, Richard Henderson, 2023/10/18
- [PATCH 51/61] target/hppa: Implement HADD, Richard Henderson, 2023/10/18
- [PATCH 53/61] target/hppa: Implement HAVG, Richard Henderson, 2023/10/18
- [PATCH 54/61] target/hppa: Implement HSHL, HSHR, Richard Henderson, 2023/10/18
- [PATCH 56/61] target/hppa: Implement MIXH, MIXW, Richard Henderson, 2023/10/18
- [PATCH 55/61] target/hppa: Implement HSHLADD, HSHRADD, Richard Henderson, 2023/10/18
- [PATCH 58/61] target/hppa: Fix interruption based on default PSW, Richard Henderson, 2023/10/18
- [PATCH 59/61] target/hppa: Precompute zero into DisasContext, Richard Henderson, 2023/10/18
- [PATCH 57/61] target/hppa: Implement PERMH,
Richard Henderson <=
- [PATCH 61/61] target/hppa: Simplify trans_dep*_imm, Richard Henderson, 2023/10/18
- [PATCH 60/61] target/hppa: Return zero for r0 from load_gpr, Richard Henderson, 2023/10/18