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[PULL v2 22/78] tests: bios-tables-test: Add test for smbios type4 threa
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From: |
Michael S. Tsirkin |
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Subject: |
[PULL v2 22/78] tests: bios-tables-test: Add test for smbios type4 thread count2 |
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Date: |
Thu, 19 Oct 2023 14:22:08 -0400 |
From: Zhao Liu <zhao1.liu@intel.com>
This tests the commit 7298fd7de5551 ("hw/smbios: Fix thread count in
type4").
In smbios_build_type_4_table() (hw/smbios/smbios.c), if the number of
threads in the socket is more than 255, then smbios type4 table encodes
threads per socket into the thread count2 field.
So for the topology in this case, there're the following considerations:
1. threads per socket should be more than 255 to ensure we could cover
the thread count2 field.
2. The original bug was that threads per socket was miscalculated, so
now we should configure as many topology levels as possible (mutiple
sockets & dies, no module since x86 hasn't supported it) to cover
more general topology scenarios, to ensure that the threads per
socket encoded in the thread count2 field is correct.
3. For the more general topology, we should also add "cpus" (presented
threads for machine) and "maxcpus" (total threads for machine) to
make sure that configuring unpluged CPUs in smp (cpus < maxcpus)
does not affect the correctness of threads per socket for thread
count2 field.
Based on these considerations, select the topology as the follow:
-smp cpus=210,maxcpus=520,sockets=2,dies=2,cores=65,threads=2
The expected thread count2 = threads per socket = threads (2)
* cores (65) * dies (2) = 260.
Suggested-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Message-Id: <20230928125943.1816922-16-zhao1.liu@linux.intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
tests/qtest/bios-tables-test.c | 31 +++++++++++++++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
index 395ed7f9ff..1e61ead539 100644
--- a/tests/qtest/bios-tables-test.c
+++ b/tests/qtest/bios-tables-test.c
@@ -96,6 +96,7 @@ typedef struct {
uint8_t smbios_core_count;
uint16_t smbios_core_count2;
uint8_t smbios_thread_count;
+ uint16_t smbios_thread_count2;
uint8_t *required_struct_types;
int required_struct_types_len;
int type4_count;
@@ -644,6 +645,7 @@ static void smbios_cpu_test(test_data *data, uint32_t addr,
uint8_t thread_count, expected_thread_count = data->smbios_thread_count;
uint16_t speed, expected_speed[2];
uint16_t core_count2, expected_core_count2 = data->smbios_core_count2;
+ uint16_t thread_count2, expected_thread_count2 =
data->smbios_thread_count2;
int offset[2];
int i;
@@ -680,6 +682,15 @@ static void smbios_cpu_test(test_data *data, uint32_t addr,
if (expected_core_count == 0xFF && expected_core_count2) {
g_assert_cmpuint(core_count2, ==, expected_core_count2);
}
+
+ thread_count2 = qtest_readw(data->qts,
+ addr + offsetof(struct smbios_type_4,
+ thread_count2));
+
+ /* Thread Count has reached its limit, checking Thread Count 2 */
+ if (expected_thread_count == 0xFF && expected_thread_count2) {
+ g_assert_cmpuint(thread_count2, ==, expected_thread_count2);
+ }
}
}
@@ -1050,6 +1061,7 @@ static void test_acpi_q35_tcg_thread_count(void)
.required_struct_types = base_required_struct_types,
.required_struct_types_len = ARRAY_SIZE(base_required_struct_types),
.smbios_thread_count = 27,
+ .smbios_thread_count2 = 27,
};
test_acpi_one("-machine smbios-entry-point-type=64 "
@@ -1058,6 +1070,23 @@ static void test_acpi_q35_tcg_thread_count(void)
free_test_data(&data);
}
+static void test_acpi_q35_tcg_thread_count2(void)
+{
+ test_data data = {
+ .machine = MACHINE_Q35,
+ .variant = ".thread-count2",
+ .required_struct_types = base_required_struct_types,
+ .required_struct_types_len = ARRAY_SIZE(base_required_struct_types),
+ .smbios_thread_count = 0xFF,
+ .smbios_thread_count2 = 260,
+ };
+
+ test_acpi_one("-machine smbios-entry-point-type=64 "
+ "-smp
cpus=210,maxcpus=520,sockets=2,dies=2,cores=65,threads=2",
+ &data);
+ free_test_data(&data);
+}
+
static void test_acpi_q35_tcg_bridge(void)
{
test_data data = {};
@@ -2228,6 +2257,8 @@ int main(int argc, char *argv[])
test_acpi_q35_tcg_core_count2);
qtest_add_func("acpi/q35/thread-count",
test_acpi_q35_tcg_thread_count);
+ qtest_add_func("acpi/q35/thread-count2",
+ test_acpi_q35_tcg_thread_count2);
}
if (qtest_has_device("virtio-iommu-pci")) {
qtest_add_func("acpi/q35/viot", test_acpi_q35_viot);
--
MST
- [PULL v2 45/78] hw/i386/pc_q35: Wire ICH9 LPC function's interrupts before its realize(), (continued)
- [PULL v2 45/78] hw/i386/pc_q35: Wire ICH9 LPC function's interrupts before its realize(), Michael S. Tsirkin, 2023/10/19
- [PULL v2 48/78] hw/isa/piix3: Create IDE controller in host device, Michael S. Tsirkin, 2023/10/19
- [PULL v2 52/78] hw/isa/piix4: Remove unused inbound ISA interrupt lines, Michael S. Tsirkin, 2023/10/19
- [PULL v2 30/78] vhost-user: call VHOST_USER_SET_VRING_ENABLE synchronously, Michael S. Tsirkin, 2023/10/19
- [PULL v2 36/78] timer/i8254: Fix one shot PIT mode, Michael S. Tsirkin, 2023/10/19
- [PULL v2 31/78] memory: initialize 'fv' in MemoryRegionCache to make Coverity happy, Michael S. Tsirkin, 2023/10/19
- [PULL v2 50/78] hw/isa/piix3: Create power management controller in host device, Michael S. Tsirkin, 2023/10/19
- [PULL v2 34/78] virtio: call ->vhost_reset_device() during reset, Michael S. Tsirkin, 2023/10/19
- [PULL v2 38/78] hw/i386/pc: Merge two if statements into one, Michael S. Tsirkin, 2023/10/19
- [PULL v2 41/78] hw/isa/piix3: Resolve redundant PIIX_NUM_PIC_IRQS, Michael S. Tsirkin, 2023/10/19
- [PULL v2 22/78] tests: bios-tables-test: Add test for smbios type4 thread count2,
Michael S. Tsirkin <=
- [PULL v2 26/78] vhost-user: factor out "vhost_user_write_sync", Michael S. Tsirkin, 2023/10/19
- [PULL v2 32/78] vhost-user: do not send RESET_OWNER on device reset, Michael S. Tsirkin, 2023/10/19
- [PULL v2 40/78] hw/i386/pc_piix: Assign PIIX3's ISA interrupts before its realize(), Michael S. Tsirkin, 2023/10/19
- [PULL v2 43/78] hw/i386/pc_piix: Remove redundant "piix3" variable, Michael S. Tsirkin, 2023/10/19
- [PULL v2 42/78] hw/i386/pc_piix: Wire PIIX3's ISA interrupts by new "isa-irqs" property, Michael S. Tsirkin, 2023/10/19
- [PULL v2 46/78] hw/isa/piix3: Wire PIC IRQs to ISA bus in host device, Michael S. Tsirkin, 2023/10/19
- [PULL v2 51/78] hw/isa/piix3: Drop the "3" from PIIX base class name, Michael S. Tsirkin, 2023/10/19
- [PULL v2 54/78] hw/isa/piix4: Rename reset control operations to match PIIX3, Michael S. Tsirkin, 2023/10/19
- [PULL v2 56/78] hw/isa/piix3: Merge hw/isa/piix4.c, Michael S. Tsirkin, 2023/10/19
- [PULL v2 59/78] hw/isa/piix: Harmonize names of reset control memory regions, Michael S. Tsirkin, 2023/10/19