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[PATCH 16/29] tcg/riscv: Support TCG_COND_TST{EQ,NE}
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From: |
Richard Henderson |
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Subject: |
[PATCH 16/29] tcg/riscv: Support TCG_COND_TST{EQ,NE} |
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Date: |
Wed, 25 Oct 2023 17:14:11 -0700 |
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/riscv/tcg-target.c.inc | 20 ++++++++++++++++++--
1 file changed, 18 insertions(+), 2 deletions(-)
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
index 34e10e77d9..3997e2f274 100644
--- a/tcg/riscv/tcg-target.c.inc
+++ b/tcg/riscv/tcg-target.c.inc
@@ -798,8 +798,14 @@ static const struct {
static void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGReg arg1,
TCGReg arg2, TCGLabel *l)
{
- RISCVInsn op = tcg_brcond_to_riscv[cond].op;
+ RISCVInsn op;
+ if (is_tst_cond(cond)) {
+ tcg_out_opc_reg(s, OPC_AND, TCG_REG_TMP0, arg1, arg2);
+ cond = tcg_tst_eqne_cond(cond);
+ }
+
+ op = tcg_brcond_to_riscv[cond].op;
tcg_debug_assert(op != 0);
if (tcg_brcond_to_riscv[cond].swap) {
@@ -827,6 +833,7 @@ static int tcg_out_setcond_int(TCGContext *s, TCGCond cond,
TCGReg ret,
case TCG_COND_GEU: /* -> LTU */
case TCG_COND_GT: /* -> LE */
case TCG_COND_GTU: /* -> LEU */
+ case TCG_COND_TSTEQ: /* -> TSTNE */
cond = tcg_invert_cond(cond);
flags ^= SETCOND_INV;
break;
@@ -886,6 +893,15 @@ static int tcg_out_setcond_int(TCGContext *s, TCGCond
cond, TCGReg ret,
}
break;
+ case TCG_COND_TSTNE:
+ flags |= SETCOND_NEZ;
+ if (c2) {
+ tcg_out_opc_imm(s, OPC_ANDI, ret, arg1, arg2);
+ } else {
+ tcg_out_opc_reg(s, OPC_AND, ret, arg1, arg2);
+ }
+ break;
+
case TCG_COND_LT:
if (c2) {
tcg_out_opc_imm(s, OPC_SLTI, ret, arg1, arg2);
@@ -1079,7 +1095,7 @@ static void tcg_out_movcond(TCGContext *s, TCGCond cond,
TCGReg ret,
int tmpflags;
TCGReg t;
- if (!have_zicond && (!c_cmp2 || cmp2 == 0)) {
+ if (!have_zicond && (!c_cmp2 || cmp2 == 0) && !is_tst_cond(cond)) {
tcg_out_movcond_br2(s, cond, ret, cmp1, cmp2,
val1, c_val1, val2, c_val2);
return;
--
2.34.1
- [PATCH 08/29] tcg/aarch64: Generate TBZ, TBNZ, (continued)
- [PATCH 08/29] tcg/aarch64: Generate TBZ, TBNZ, Richard Henderson, 2023/10/25
- [PULL 05/94] configs: Enable MTTCG for sparc, sparc64, Richard Henderson, 2023/10/25
- [PATCH 10/29] tcg/i386: Pass x86 condition codes to tcg_out_cmov, Richard Henderson, 2023/10/25
- [PATCH 12/29] tcg/i386: Add rexw argument to tcg_out_testi, Richard Henderson, 2023/10/25
- [PATCH 14/29] tcg/loongarch64: Support TCG_COND_TST{EQ,NE}, Richard Henderson, 2023/10/25
- [PULL 14/94] target/sparc: Move BPr to decodetree, Richard Henderson, 2023/10/25
- [PULL 15/94] target/sparc: Move FBPfcc and FBfcc to decodetree, Richard Henderson, 2023/10/25
- [PULL 18/94] target/sparc: Merge gen_branch_[an] with only caller, Richard Henderson, 2023/10/25
- [PATCH 19/29] tcg/sparc64: Pass TCGCond to tcg_out_cmp, Richard Henderson, 2023/10/25
- [PATCH 15/29] tcg/mips: Support TCG_COND_TST{EQ,NE}, Richard Henderson, 2023/10/25
- [PATCH 16/29] tcg/riscv: Support TCG_COND_TST{EQ,NE},
Richard Henderson <=
- [PULL 13/94] target/sparc: Move BPcc and Bicc to decodetree, Richard Henderson, 2023/10/25
- [PULL 11/94] target/sparc: Define AM_CHECK for sparc32, Richard Henderson, 2023/10/25
- [PULL 12/94] target/sparc: Move CALL to decodetree, Richard Henderson, 2023/10/25
- [PULL 06/94] target/sparc: Define features via cpu-feature.h.inc, Richard Henderson, 2023/10/25
- [PATCH 13/29] tcg/i386: Support TCG_COND_TST{EQ,NE}, Richard Henderson, 2023/10/25
- [PATCH 06/29] tcg/optimize: Handle TCG_COND_TST{EQ,NE}, Richard Henderson, 2023/10/25