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[PULL 41/41] hw/net/cadence_gem: enforce 32 bits variable size for CRC
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From: |
Peter Maydell |
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Subject: |
[PULL 41/41] hw/net/cadence_gem: enforce 32 bits variable size for CRC |
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Date: |
Fri, 27 Oct 2023 15:39:42 +0100 |
From: Luc Michel <luc.michel@amd.com>
The CRC was stored in an unsigned variable in gem_receive. Change it for
a uint32_t to ensure we have the correct variable size here.
Signed-off-by: Luc Michel <luc.michel@amd.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: sai.pavan.boddu@amd.com
Message-id: 20231017194422.4124691-12-luc.michel@amd.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/net/cadence_gem.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index 06a101bfcd4..5b989f5b523 100644
--- a/hw/net/cadence_gem.c
+++ b/hw/net/cadence_gem.c
@@ -1105,7 +1105,7 @@ static ssize_t gem_receive(NetClientState *nc, const
uint8_t *buf, size_t size)
if (FIELD_EX32(s->regs[R_NWCFG], NWCFG, FCS_REMOVE)) {
rxbuf_ptr = (void *)buf;
} else {
- unsigned crc_val;
+ uint32_t crc_val;
if (size > MAX_FRAME_SIZE - sizeof(crc_val)) {
size = MAX_FRAME_SIZE - sizeof(crc_val);
--
2.34.1
- [PULL 26/41] hw/intc/pxa2xx: Pass CPU reference using QOM link property, (continued)
- [PULL 26/41] hw/intc/pxa2xx: Pass CPU reference using QOM link property, Peter Maydell, 2023/10/27
- [PULL 33/41] hw/net/cadence_gem: use FIELD to describe NWCTRL register fields, Peter Maydell, 2023/10/27
- [PULL 14/41] hw/arm/fsl-imx31: Remove 'hw/arm/boot.h' from header, Peter Maydell, 2023/10/27
- [PULL 25/41] hw/intc/pxa2xx: Convert to Resettable interface, Peter Maydell, 2023/10/27
- [PULL 39/41] hw/net/cadence_gem: use FIELD to describe PHYMNTNC register fields, Peter Maydell, 2023/10/27
- [PULL 34/41] hw/net/cadence_gem: use FIELD to describe NWCFG register fields, Peter Maydell, 2023/10/27
- [PULL 37/41] hw/net/cadence_gem: use FIELD to describe IRQ register fields, Peter Maydell, 2023/10/27
- [PULL 31/41] hw/net/cadence_gem: use REG32 macro for register definitions, Peter Maydell, 2023/10/27
- [PULL 35/41] hw/net/cadence_gem: use FIELD to describe DMACFG register fields, Peter Maydell, 2023/10/27
- [PULL 27/41] hw/intc/pxa2xx: Factor pxa2xx_pic_realize() out of pxa2xx_pic_init(), Peter Maydell, 2023/10/27
- [PULL 41/41] hw/net/cadence_gem: enforce 32 bits variable size for CRC,
Peter Maydell <=
- [PULL 28/41] hw/arm/pxa2xx: Realize PXA2XX_I2C device before accessing it, Peter Maydell, 2023/10/27
- [PULL 20/41] hw/sd/pxa2xx: Realize sysbus device before accessing it, Peter Maydell, 2023/10/27
- [PULL 38/41] hw/net/cadence_gem: use FIELD to describe DESCONF6 register fields, Peter Maydell, 2023/10/27
- [PULL 21/41] hw/sd/pxa2xx: Do not open-code sysbus_create_simple(), Peter Maydell, 2023/10/27
- [PULL 07/41] target/arm: Move ID_AA64PFR* tests together, Peter Maydell, 2023/10/27
- [PULL 40/41] hw/net/cadence_gem: perform PHY access on write only, Peter Maydell, 2023/10/27
- [PULL 36/41] hw/net/cadence_gem: use FIELD to describe [TX|RX]STATUS register fields, Peter Maydell, 2023/10/27
- Re: [PULL 00/41] target-arm queue, Stefan Hajnoczi, 2023/10/29