[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH v3 27/88] target/hppa: Pass DisasContext to copy_iaoq_entry
|
From: |
Richard Henderson |
|
Subject: |
[PATCH v3 27/88] target/hppa: Pass DisasContext to copy_iaoq_entry |
|
Date: |
Wed, 1 Nov 2023 18:29:15 -0700 |
Interface change only, no functional effect.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/translate.c | 39 ++++++++++++++++++++-------------------
1 file changed, 20 insertions(+), 19 deletions(-)
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 4e0bc48b09..e342cc1d08 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -717,7 +717,8 @@ static target_ureg gva_offset_mask(DisasContext *ctx)
: MAKE_64BIT_MASK(0, 32));
}
-static void copy_iaoq_entry(TCGv_reg dest, target_ureg ival, TCGv_reg vval)
+static void copy_iaoq_entry(DisasContext *ctx, TCGv_reg dest,
+ target_ureg ival, TCGv_reg vval)
{
if (unlikely(ival == -1)) {
tcg_gen_mov_reg(dest, vval);
@@ -738,8 +739,8 @@ static void gen_excp_1(int exception)
static void gen_excp(DisasContext *ctx, int exception)
{
- copy_iaoq_entry(cpu_iaoq_f, ctx->iaoq_f, cpu_iaoq_f);
- copy_iaoq_entry(cpu_iaoq_b, ctx->iaoq_b, cpu_iaoq_b);
+ copy_iaoq_entry(ctx, cpu_iaoq_f, ctx->iaoq_f, cpu_iaoq_f);
+ copy_iaoq_entry(ctx, cpu_iaoq_b, ctx->iaoq_b, cpu_iaoq_b);
nullify_save(ctx);
gen_excp_1(exception);
ctx->base.is_jmp = DISAS_NORETURN;
@@ -795,8 +796,8 @@ static void gen_goto_tb(DisasContext *ctx, int which,
tcg_gen_movi_reg(cpu_iaoq_b, b);
tcg_gen_exit_tb(ctx->base.tb, which);
} else {
- copy_iaoq_entry(cpu_iaoq_f, f, cpu_iaoq_b);
- copy_iaoq_entry(cpu_iaoq_b, b, ctx->iaoq_n_var);
+ copy_iaoq_entry(ctx, cpu_iaoq_f, f, cpu_iaoq_b);
+ copy_iaoq_entry(ctx, cpu_iaoq_b, b, ctx->iaoq_n_var);
tcg_gen_lookup_and_goto_ptr();
}
}
@@ -1752,7 +1753,7 @@ static bool do_dbranch(DisasContext *ctx, target_ureg
dest,
{
if (ctx->null_cond.c == TCG_COND_NEVER && ctx->null_lab == NULL) {
if (link != 0) {
- copy_iaoq_entry(cpu_gr[link], ctx->iaoq_n, ctx->iaoq_n_var);
+ copy_iaoq_entry(ctx, cpu_gr[link], ctx->iaoq_n, ctx->iaoq_n_var);
}
ctx->iaoq_n = dest;
if (is_n) {
@@ -1762,7 +1763,7 @@ static bool do_dbranch(DisasContext *ctx, target_ureg
dest,
nullify_over(ctx);
if (link != 0) {
- copy_iaoq_entry(cpu_gr[link], ctx->iaoq_n, ctx->iaoq_n_var);
+ copy_iaoq_entry(ctx, cpu_gr[link], ctx->iaoq_n, ctx->iaoq_n_var);
}
if (is_n && use_nullify_skip(ctx)) {
@@ -1860,7 +1861,7 @@ static bool do_ibranch(DisasContext *ctx, TCGv_reg dest,
if (ctx->null_cond.c == TCG_COND_NEVER) {
if (link != 0) {
- copy_iaoq_entry(cpu_gr[link], ctx->iaoq_n, ctx->iaoq_n_var);
+ copy_iaoq_entry(ctx, cpu_gr[link], ctx->iaoq_n, ctx->iaoq_n_var);
}
next = tcg_temp_new();
tcg_gen_mov_reg(next, dest);
@@ -1906,7 +1907,7 @@ static bool do_ibranch(DisasContext *ctx, TCGv_reg dest,
tmp = tcg_temp_new();
next = tcg_temp_new();
- copy_iaoq_entry(tmp, ctx->iaoq_n, ctx->iaoq_n_var);
+ copy_iaoq_entry(ctx, tmp, ctx->iaoq_n, ctx->iaoq_n_var);
tcg_gen_movcond_reg(c, next, a0, a1, tmp, dest);
ctx->iaoq_n = -1;
ctx->iaoq_n_var = next;
@@ -2643,8 +2644,8 @@ static bool trans_or(DisasContext *ctx, arg_rrr_cf *a)
nullify_over(ctx);
/* Advance the instruction queue. */
- copy_iaoq_entry(cpu_iaoq_f, ctx->iaoq_b, cpu_iaoq_b);
- copy_iaoq_entry(cpu_iaoq_b, ctx->iaoq_n, ctx->iaoq_n_var);
+ copy_iaoq_entry(ctx, cpu_iaoq_f, ctx->iaoq_b, cpu_iaoq_b);
+ copy_iaoq_entry(ctx, cpu_iaoq_b, ctx->iaoq_n, ctx->iaoq_n_var);
nullify_set(ctx, 0);
/* Tell the qemu main loop to halt until this cpu has work. */
@@ -3433,7 +3434,7 @@ static bool trans_be(DisasContext *ctx, arg_be *a)
load_spr(ctx, new_spc, a->sp);
if (a->l) {
- copy_iaoq_entry(cpu_gr[31], ctx->iaoq_n, ctx->iaoq_n_var);
+ copy_iaoq_entry(ctx, cpu_gr[31], ctx->iaoq_n, ctx->iaoq_n_var);
tcg_gen_mov_i64(cpu_sr[0], cpu_iasq_f);
}
if (a->n && use_nullify_skip(ctx)) {
@@ -3442,7 +3443,7 @@ static bool trans_be(DisasContext *ctx, arg_be *a)
tcg_gen_mov_i64(cpu_iasq_f, new_spc);
tcg_gen_mov_i64(cpu_iasq_b, cpu_iasq_f);
} else {
- copy_iaoq_entry(cpu_iaoq_f, ctx->iaoq_b, cpu_iaoq_b);
+ copy_iaoq_entry(ctx, cpu_iaoq_f, ctx->iaoq_b, cpu_iaoq_b);
if (ctx->iaoq_b == -1) {
tcg_gen_mov_i64(cpu_iasq_f, cpu_iasq_b);
}
@@ -3556,14 +3557,14 @@ static bool trans_bve(DisasContext *ctx, arg_bve *a)
nullify_over(ctx);
dest = do_ibranch_priv(ctx, load_gpr(ctx, a->b));
- copy_iaoq_entry(cpu_iaoq_f, ctx->iaoq_b, cpu_iaoq_b);
+ copy_iaoq_entry(ctx, cpu_iaoq_f, ctx->iaoq_b, cpu_iaoq_b);
if (ctx->iaoq_b == -1) {
tcg_gen_mov_i64(cpu_iasq_f, cpu_iasq_b);
}
- copy_iaoq_entry(cpu_iaoq_b, -1, dest);
+ copy_iaoq_entry(ctx, cpu_iaoq_b, -1, dest);
tcg_gen_mov_i64(cpu_iasq_b, space_select(ctx, 0, dest));
if (a->l) {
- copy_iaoq_entry(cpu_gr[a->l], ctx->iaoq_n, ctx->iaoq_n_var);
+ copy_iaoq_entry(ctx, cpu_gr[a->l], ctx->iaoq_n, ctx->iaoq_n_var);
}
nullify_set(ctx, a->n);
tcg_gen_lookup_and_goto_ptr();
@@ -4218,7 +4219,7 @@ static void hppa_tr_translate_insn(DisasContextBase
*dcbase, CPUState *cs)
case DISAS_IAQ_N_STALE_EXIT:
if (ctx->iaoq_f == -1) {
tcg_gen_mov_reg(cpu_iaoq_f, cpu_iaoq_b);
- copy_iaoq_entry(cpu_iaoq_b, ctx->iaoq_n, ctx->iaoq_n_var);
+ copy_iaoq_entry(ctx, cpu_iaoq_b, ctx->iaoq_n, ctx->iaoq_n_var);
#ifndef CONFIG_USER_ONLY
tcg_gen_mov_i64(cpu_iasq_f, cpu_iasq_b);
#endif
@@ -4247,8 +4248,8 @@ static void hppa_tr_tb_stop(DisasContextBase *dcbase,
CPUState *cs)
case DISAS_TOO_MANY:
case DISAS_IAQ_N_STALE:
case DISAS_IAQ_N_STALE_EXIT:
- copy_iaoq_entry(cpu_iaoq_f, ctx->iaoq_f, cpu_iaoq_f);
- copy_iaoq_entry(cpu_iaoq_b, ctx->iaoq_b, cpu_iaoq_b);
+ copy_iaoq_entry(ctx, cpu_iaoq_f, ctx->iaoq_f, cpu_iaoq_f);
+ copy_iaoq_entry(ctx, cpu_iaoq_b, ctx->iaoq_b, cpu_iaoq_b);
nullify_save(ctx);
/* FALLTHRU */
case DISAS_IAQ_N_UPDATED:
--
2.34.1
- [PATCH v3 24/88] target/hppa: Handle absolute addresses for pa2.0, (continued)
- [PATCH v3 24/88] target/hppa: Handle absolute addresses for pa2.0, Richard Henderson, 2023/11/01
- [PATCH v3 21/88] target/hppa: Implement cpu_list, Richard Henderson, 2023/11/01
- [PATCH v3 26/88] target/hppa: Fix hppa64 addressing, Richard Henderson, 2023/11/01
- [PATCH v3 31/88] target/hppa: sar register allows only 5 bits on 32-bit CPU, Richard Henderson, 2023/11/01
- [PATCH v3 29/88] target/hppa: Use copy_iaoq_entry for link in do_ibranch, Richard Henderson, 2023/11/01
- [PATCH v3 33/88] target/hppa: Pass d to do_sub_cond, Richard Henderson, 2023/11/01
- [PATCH v3 34/88] target/hppa: Pass d to do_log_cond, Richard Henderson, 2023/11/01
- [PATCH v3 30/88] target/hppa: Mask inputs in copy_iaoq_entry, Richard Henderson, 2023/11/01
- [PATCH v3 08/88] tcg: Improve expansion of deposit into a constant, Richard Henderson, 2023/11/01
- [PATCH v3 20/88] target/hppa: Make HPPA_BTLB_ENTRIES variable, Richard Henderson, 2023/11/01
- [PATCH v3 27/88] target/hppa: Pass DisasContext to copy_iaoq_entry,
Richard Henderson <=
- [PATCH v3 28/88] target/hppa: Always use copy_iaoq_entry to set cpu_iaoq_[fb], Richard Henderson, 2023/11/01
- [PATCH v3 32/88] target/hppa: Pass d to do_cond, Richard Henderson, 2023/11/01
- [PATCH v3 37/88] linux-user/hppa: Fixes for TARGET_ABI32, Richard Henderson, 2023/11/01
- [PATCH v3 35/88] target/hppa: Pass d to do_sed_cond, Richard Henderson, 2023/11/01
- [PATCH v3 36/88] target/hppa: Pass d to do_unit_cond, Richard Henderson, 2023/11/01
- [PATCH v3 38/88] target/hppa: Drop attempted gdbstub support for hppa64, Richard Henderson, 2023/11/01
- [PATCH v3 39/88] target/hppa: Remove TARGET_HPPA64, Richard Henderson, 2023/11/01
- [PATCH v3 40/88] target/hppa: Decode d for logical instructions, Richard Henderson, 2023/11/01
- [PATCH v3 41/88] target/hppa: Decode d for unit instructions, Richard Henderson, 2023/11/01
- [PATCH v3 43/88] target/hppa: Decode d for add instructions, Richard Henderson, 2023/11/01