[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 28/33] hw/char/stm32f2xx_usart: Update IRQ when DR is written
|
From: |
Peter Maydell |
|
Subject: |
[PULL 28/33] hw/char/stm32f2xx_usart: Update IRQ when DR is written |
|
Date: |
Thu, 2 Nov 2023 17:38:30 +0000 |
From: Hans-Erik Floryd <hans-erik.floryd@rt-labs.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Hans-Erik Floryd <hans-erik.floryd@rt-labs.com>
Message-id: 20231030151528.1138131-3-hans-erik.floryd@rt-labs.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/char/stm32f2xx_usart.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/char/stm32f2xx_usart.c b/hw/char/stm32f2xx_usart.c
index 519d3461a33..8753afeb2b8 100644
--- a/hw/char/stm32f2xx_usart.c
+++ b/hw/char/stm32f2xx_usart.c
@@ -168,6 +168,7 @@ static void stm32f2xx_usart_write(void *opaque, hwaddr addr,
clear TC by writing 0 to the SR register, so set it again
on each write. */
s->usart_sr |= USART_SR_TC;
+ stm32f2xx_update_irq(s);
}
return;
case USART_BRR:
--
2.34.1
- [PULL 15/33] docs/specs/vmgenid: Convert to rST, (continued)
- [PULL 15/33] docs/specs/vmgenid: Convert to rST, Peter Maydell, 2023/11/02
- [PULL 11/33] docs/specs/pvpanic: Convert to rST, Peter Maydell, 2023/11/02
- [PULL 17/33] hw/arm/pxa2xx_gpio: Pass CPU using QOM link property, Peter Maydell, 2023/11/02
- [PULL 18/33] hw/watchdog/wdt_imx2: Trace MMIO access, Peter Maydell, 2023/11/02
- [PULL 08/33] docs/specs/vmw_pvscsi-spec: Convert to rST, Peter Maydell, 2023/11/02
- [PULL 10/33] docs/specs/ivshmem-spec: Convert to rST, Peter Maydell, 2023/11/02
- [PULL 14/33] docs/specs/vmcoreinfo: Convert to rST, Peter Maydell, 2023/11/02
- [PULL 19/33] hw/watchdog/wdt_imx2: Trace timer activity, Peter Maydell, 2023/11/02
- [PULL 24/33] linux-user: Report AArch64 hwcap2 fields above bit 31, Peter Maydell, 2023/11/02
- [PULL 30/33] target/arm: Correctly propagate stage 1 BTI guarded bit in a two-stage walk, Peter Maydell, 2023/11/02
- [PULL 28/33] hw/char/stm32f2xx_usart: Update IRQ when DR is written,
Peter Maydell <=
- [PULL 31/33] hw/misc: Introduce AMD/Xilix Versal TRNG device, Peter Maydell, 2023/11/02
- [PULL 32/33] hw/arm: xlnx-versal-virt: Add AMD/Xilinx TRNG device, Peter Maydell, 2023/11/02
- [PULL 12/33] docs/specs/standard-vga: Convert to rST, Peter Maydell, 2023/11/02
- [PULL 20/33] hw/misc/imx7_snvs: Trace MMIO access, Peter Maydell, 2023/11/02
- [PULL 02/33] hw/input/stellaris_input: Rename to stellaris_gamepad, Peter Maydell, 2023/11/02
- [PULL 33/33] tests/qtest: Introduce tests for AMD/Xilinx Versal TRNG device, Peter Maydell, 2023/11/02
- [PULL 22/33] hw/i2c/pm_smbus: Convert DPRINTF to trace events, Peter Maydell, 2023/11/02
- [PULL 26/33] target/arm: Fix SVE STR increment, Peter Maydell, 2023/11/02
- [PULL 29/33] hw/char/stm32f2xx_usart: Add more definitions for CR1 register, Peter Maydell, 2023/11/02
- [PULL 13/33] docs/specs/virt-ctlr: Convert to rST, Peter Maydell, 2023/11/02