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[PULL 29/33] hw/char/stm32f2xx_usart: Add more definitions for CR1 regis
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From: |
Peter Maydell |
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Subject: |
[PULL 29/33] hw/char/stm32f2xx_usart: Add more definitions for CR1 register |
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Date: |
Thu, 2 Nov 2023 17:38:31 +0000 |
From: Hans-Erik Floryd <hans-erik.floryd@rt-labs.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Hans-Erik Floryd <hans-erik.floryd@rt-labs.com>
Message-id: 20231030151528.1138131-4-hans-erik.floryd@rt-labs.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/hw/char/stm32f2xx_usart.h | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/include/hw/char/stm32f2xx_usart.h
b/include/hw/char/stm32f2xx_usart.h
index 65bcc85470d..fdfa7424a70 100644
--- a/include/hw/char/stm32f2xx_usart.h
+++ b/include/hw/char/stm32f2xx_usart.h
@@ -48,10 +48,12 @@
#define USART_SR_TC (1 << 6)
#define USART_SR_RXNE (1 << 5)
-#define USART_CR1_UE (1 << 13)
-#define USART_CR1_RXNEIE (1 << 5)
-#define USART_CR1_TE (1 << 3)
-#define USART_CR1_RE (1 << 2)
+#define USART_CR1_UE (1 << 13)
+#define USART_CR1_TXEIE (1 << 7)
+#define USART_CR1_TCEIE (1 << 6)
+#define USART_CR1_RXNEIE (1 << 5)
+#define USART_CR1_TE (1 << 3)
+#define USART_CR1_RE (1 << 2)
#define TYPE_STM32F2XX_USART "stm32f2xx-usart"
OBJECT_DECLARE_SIMPLE_TYPE(STM32F2XXUsartState, STM32F2XX_USART)
--
2.34.1
- [PULL 30/33] target/arm: Correctly propagate stage 1 BTI guarded bit in a two-stage walk, (continued)
- [PULL 30/33] target/arm: Correctly propagate stage 1 BTI guarded bit in a two-stage walk, Peter Maydell, 2023/11/02
- [PULL 28/33] hw/char/stm32f2xx_usart: Update IRQ when DR is written, Peter Maydell, 2023/11/02
- [PULL 31/33] hw/misc: Introduce AMD/Xilix Versal TRNG device, Peter Maydell, 2023/11/02
- [PULL 32/33] hw/arm: xlnx-versal-virt: Add AMD/Xilinx TRNG device, Peter Maydell, 2023/11/02
- [PULL 12/33] docs/specs/standard-vga: Convert to rST, Peter Maydell, 2023/11/02
- [PULL 20/33] hw/misc/imx7_snvs: Trace MMIO access, Peter Maydell, 2023/11/02
- [PULL 02/33] hw/input/stellaris_input: Rename to stellaris_gamepad, Peter Maydell, 2023/11/02
- [PULL 33/33] tests/qtest: Introduce tests for AMD/Xilinx Versal TRNG device, Peter Maydell, 2023/11/02
- [PULL 22/33] hw/i2c/pm_smbus: Convert DPRINTF to trace events, Peter Maydell, 2023/11/02
- [PULL 26/33] target/arm: Fix SVE STR increment, Peter Maydell, 2023/11/02
- [PULL 29/33] hw/char/stm32f2xx_usart: Add more definitions for CR1 register,
Peter Maydell <=
- [PULL 13/33] docs/specs/virt-ctlr: Convert to rST, Peter Maydell, 2023/11/02
- [PULL 25/33] target/arm: Make FEAT_MOPS SET* insns handle Xs == XZR correctly, Peter Maydell, 2023/11/02
- [PULL 16/33] MAINTAINERS: Make sure that gicv3_internal.h is covered, too, Peter Maydell, 2023/11/02
- [PULL 04/33] qdev: Add qdev_prop_set_array(), Peter Maydell, 2023/11/02
- [PULL 21/33] hw/misc/imx6_ccm: Convert DPRINTF to trace events, Peter Maydell, 2023/11/02
- [PULL 23/33] target/arm: Enable FEAT_MOPS insns in user-mode emulation, Peter Maydell, 2023/11/02
- [PULL 27/33] hw/char/stm32f2xx_usart: Extract common IRQ update code to update_irq(), Peter Maydell, 2023/11/02
- Re: [PULL 00/33] target-arm queue, Stefan Hajnoczi, 2023/11/02