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[PULL 25/33] target/arm: Make FEAT_MOPS SET* insns handle Xs == XZR corr
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From: |
Peter Maydell |
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Subject: |
[PULL 25/33] target/arm: Make FEAT_MOPS SET* insns handle Xs == XZR correctly |
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Date: |
Thu, 2 Nov 2023 17:38:27 +0000 |
Most of the registers used by the FEAT_MOPS instructions cannot use
31 as a register field value; this is CONSTRAINED UNPREDICTABLE to
NOP or UNDEF (we UNDEF). However, it is permitted for the "source
value" register for the memset insns SET* to be 31, which (as usual
for most data-processing insns) means it should be the zero register
XZR. We forgot to handle this case, with the effect that trying to
set memory to zero with a "SET* Xd, Xn, XZR" sets the memory to
the value that happens to be in the low byte of SP.
Handle XZR when getting the SET* data value from the register file.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20231030174000.3792225-4-peter.maydell@linaro.org
---
target/arm/tcg/helper-a64.c | 15 ++++++++++++---
1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c
index 84f54750fc2..ce4800b8d13 100644
--- a/target/arm/tcg/helper-a64.c
+++ b/target/arm/tcg/helper-a64.c
@@ -1206,6 +1206,15 @@ static void check_setg_alignment(CPUARMState *env,
uint64_t ptr, uint64_t size,
}
}
+static uint64_t arm_reg_or_xzr(CPUARMState *env, int reg)
+{
+ /*
+ * Runtime equivalent of cpu_reg() -- return the CPU register value,
+ * for contexts when index 31 means XZR (not SP).
+ */
+ return reg == 31 ? 0 : env->xregs[reg];
+}
+
/*
* For the Memory Set operation, our implementation chooses
* always to use "option A", where we update Xd to the final
@@ -1226,7 +1235,7 @@ static void do_setp(CPUARMState *env, uint32_t syndrome,
uint32_t mtedesc,
int rd = mops_destreg(syndrome);
int rs = mops_srcreg(syndrome);
int rn = mops_sizereg(syndrome);
- uint8_t data = env->xregs[rs];
+ uint8_t data = arm_reg_or_xzr(env, rs);
uint32_t memidx = FIELD_EX32(mtedesc, MTEDESC, MIDX);
uint64_t toaddr = env->xregs[rd];
uint64_t setsize = env->xregs[rn];
@@ -1286,7 +1295,7 @@ static void do_setm(CPUARMState *env, uint32_t syndrome,
uint32_t mtedesc,
int rd = mops_destreg(syndrome);
int rs = mops_srcreg(syndrome);
int rn = mops_sizereg(syndrome);
- uint8_t data = env->xregs[rs];
+ uint8_t data = arm_reg_or_xzr(env, rs);
uint64_t toaddr = env->xregs[rd] + env->xregs[rn];
uint64_t setsize = -env->xregs[rn];
uint32_t memidx = FIELD_EX32(mtedesc, MTEDESC, MIDX);
@@ -1349,7 +1358,7 @@ static void do_sete(CPUARMState *env, uint32_t syndrome,
uint32_t mtedesc,
int rd = mops_destreg(syndrome);
int rs = mops_srcreg(syndrome);
int rn = mops_sizereg(syndrome);
- uint8_t data = env->xregs[rs];
+ uint8_t data = arm_reg_or_xzr(env, rs);
uint64_t toaddr = env->xregs[rd] + env->xregs[rn];
uint64_t setsize = -env->xregs[rn];
uint32_t memidx = FIELD_EX32(mtedesc, MTEDESC, MIDX);
--
2.34.1
- [PULL 31/33] hw/misc: Introduce AMD/Xilix Versal TRNG device, (continued)
- [PULL 31/33] hw/misc: Introduce AMD/Xilix Versal TRNG device, Peter Maydell, 2023/11/02
- [PULL 32/33] hw/arm: xlnx-versal-virt: Add AMD/Xilinx TRNG device, Peter Maydell, 2023/11/02
- [PULL 12/33] docs/specs/standard-vga: Convert to rST, Peter Maydell, 2023/11/02
- [PULL 20/33] hw/misc/imx7_snvs: Trace MMIO access, Peter Maydell, 2023/11/02
- [PULL 02/33] hw/input/stellaris_input: Rename to stellaris_gamepad, Peter Maydell, 2023/11/02
- [PULL 33/33] tests/qtest: Introduce tests for AMD/Xilinx Versal TRNG device, Peter Maydell, 2023/11/02
- [PULL 22/33] hw/i2c/pm_smbus: Convert DPRINTF to trace events, Peter Maydell, 2023/11/02
- [PULL 26/33] target/arm: Fix SVE STR increment, Peter Maydell, 2023/11/02
- [PULL 29/33] hw/char/stm32f2xx_usart: Add more definitions for CR1 register, Peter Maydell, 2023/11/02
- [PULL 13/33] docs/specs/virt-ctlr: Convert to rST, Peter Maydell, 2023/11/02
- [PULL 25/33] target/arm: Make FEAT_MOPS SET* insns handle Xs == XZR correctly,
Peter Maydell <=
- [PULL 16/33] MAINTAINERS: Make sure that gicv3_internal.h is covered, too, Peter Maydell, 2023/11/02
- [PULL 04/33] qdev: Add qdev_prop_set_array(), Peter Maydell, 2023/11/02
- [PULL 21/33] hw/misc/imx6_ccm: Convert DPRINTF to trace events, Peter Maydell, 2023/11/02
- [PULL 23/33] target/arm: Enable FEAT_MOPS insns in user-mode emulation, Peter Maydell, 2023/11/02
- [PULL 27/33] hw/char/stm32f2xx_usart: Extract common IRQ update code to update_irq(), Peter Maydell, 2023/11/02
- Re: [PULL 00/33] target-arm queue, Stefan Hajnoczi, 2023/11/02