[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 12/49] docs/system/riscv: update 'virt' machine core limit
|
From: |
Alistair Francis |
|
Subject: |
[PULL 12/49] docs/system/riscv: update 'virt' machine core limit |
|
Date: |
Tue, 7 Nov 2023 12:29:08 +1000 |
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
The 'virt' RISC-V machine does not have a 8 core limit. The current
limit is set in include/hw/riscv/virt.h, VIRT_CPUS_MAX, set to 512 at
this moment.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1945
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20231020200247.334403-2-dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
docs/system/riscv/virt.rst | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/docs/system/riscv/virt.rst b/docs/system/riscv/virt.rst
index f9a2eac544..f5fa7b8b29 100644
--- a/docs/system/riscv/virt.rst
+++ b/docs/system/riscv/virt.rst
@@ -12,7 +12,7 @@ Supported devices
The ``virt`` machine supports the following devices:
-* Up to 8 generic RV32GC/RV64GC cores, with optional extensions
+* Up to 512 generic RV32GC/RV64GC cores, with optional extensions
* Core Local Interruptor (CLINT)
* Platform-Level Interrupt Controller (PLIC)
* CFI parallel NOR flash memory
--
2.41.0
- [PULL 01/49] target/riscv: rename ext_ifencei to ext_zifencei, (continued)
- [PULL 01/49] target/riscv: rename ext_ifencei to ext_zifencei, Alistair Francis, 2023/11/06
- [PULL 02/49] target/riscv: rename ext_icsr to ext_zicsr, Alistair Francis, 2023/11/06
- [PULL 03/49] target/riscv: rename ext_icbom to ext_zicbom, Alistair Francis, 2023/11/06
- [PULL 04/49] target/riscv: rename ext_icboz to ext_zicboz, Alistair Francis, 2023/11/06
- [PULL 05/49] target/riscv: Without H-mode mask all HS mode inturrupts in mie., Alistair Francis, 2023/11/06
- [PULL 06/49] target/riscv: Check for async flag in case of RISCV_EXCP_SEMIHOST., Alistair Francis, 2023/11/06
- [PULL 07/49] target/riscv: Set VS* bits to one in mideleg when H-Ext is enabled, Alistair Francis, 2023/11/06
- [PULL 08/49] target/riscv: Split interrupt logic from riscv_cpu_update_mip., Alistair Francis, 2023/11/06
- [PULL 09/49] target/riscv: Add M-mode virtual interrupt and IRQ filtering support., Alistair Francis, 2023/11/06
- [PULL 10/49] target/riscv: Add HS-mode virtual interrupt and IRQ filtering support., Alistair Francis, 2023/11/06
- [PULL 12/49] docs/system/riscv: update 'virt' machine core limit,
Alistair Francis <=
- [PULL 13/49] target/riscv/kvm/kvm-cpu.c: add missing property getters(), Alistair Francis, 2023/11/06
- [PULL 11/49] linux-user/riscv: change default cpu to 'max', Alistair Francis, 2023/11/06
- [PULL 14/49] qapi,risc-v: add query-cpu-model-expansion, Alistair Francis, 2023/11/06
- [PULL 16/49] target/riscv: handle custom props in qmp_query_cpu_model_expansion, Alistair Francis, 2023/11/06
- [PULL 15/49] target/riscv/tcg: add tcg_cpu_finalize_features(), Alistair Francis, 2023/11/06
- [PULL 17/49] target/riscv: add riscv_cpu_accelerator_compatible(), Alistair Francis, 2023/11/06
- [PULL 20/49] target/riscv: pmp: Clear pmp/smepmp bits on reset, Alistair Francis, 2023/11/06
- [PULL 21/49] target/riscv: pmp: Ignore writes when RW=01, Alistair Francis, 2023/11/06
- [PULL 18/49] target/riscv/riscv-qmp-cmds.c: check CPU accel in query-cpu-model-expansion, Alistair Francis, 2023/11/06
- [PULL 22/49] target/riscv: add zicntr extension flag for TCG, Alistair Francis, 2023/11/06