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[PULL 11/49] linux-user/riscv: change default cpu to 'max'
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From: |
Alistair Francis |
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Subject: |
[PULL 11/49] linux-user/riscv: change default cpu to 'max' |
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Date: |
Tue, 7 Nov 2023 12:29:07 +1000 |
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Commit f57d5f8004 deprecated the 'any' CPU type but failed to change the
default CPU for linux-user. The result is that all linux-users
invocations that doesn't specify a different CPU started to show a
deprecation warning:
$ ./build/qemu-riscv64 ./foo-novect.out
qemu-riscv64: warning: The 'any' CPU is deprecated and will be removed in the
future.
Change the default CPU for RISC-V linux-user from 'any' to 'max'.
Reported-by: Richard Henderson <richard.henderson@linaro.org>
Fixes: f57d5f8004 ("target/riscv: deprecate the 'any' CPU type")
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20231020074501.283063-1-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
linux-user/riscv/target_elf.h | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/linux-user/riscv/target_elf.h b/linux-user/riscv/target_elf.h
index 9dd65652ee..dedd5956f3 100644
--- a/linux-user/riscv/target_elf.h
+++ b/linux-user/riscv/target_elf.h
@@ -9,7 +9,6 @@
#define RISCV_TARGET_ELF_H
static inline const char *cpu_get_model(uint32_t eflags)
{
- /* TYPE_RISCV_CPU_ANY */
- return "any";
+ return "max";
}
#endif
--
2.41.0
- [PULL 03/49] target/riscv: rename ext_icbom to ext_zicbom, (continued)
- [PULL 03/49] target/riscv: rename ext_icbom to ext_zicbom, Alistair Francis, 2023/11/06
- [PULL 04/49] target/riscv: rename ext_icboz to ext_zicboz, Alistair Francis, 2023/11/06
- [PULL 05/49] target/riscv: Without H-mode mask all HS mode inturrupts in mie., Alistair Francis, 2023/11/06
- [PULL 06/49] target/riscv: Check for async flag in case of RISCV_EXCP_SEMIHOST., Alistair Francis, 2023/11/06
- [PULL 07/49] target/riscv: Set VS* bits to one in mideleg when H-Ext is enabled, Alistair Francis, 2023/11/06
- [PULL 08/49] target/riscv: Split interrupt logic from riscv_cpu_update_mip., Alistair Francis, 2023/11/06
- [PULL 09/49] target/riscv: Add M-mode virtual interrupt and IRQ filtering support., Alistair Francis, 2023/11/06
- [PULL 10/49] target/riscv: Add HS-mode virtual interrupt and IRQ filtering support., Alistair Francis, 2023/11/06
- [PULL 12/49] docs/system/riscv: update 'virt' machine core limit, Alistair Francis, 2023/11/06
- [PULL 13/49] target/riscv/kvm/kvm-cpu.c: add missing property getters(), Alistair Francis, 2023/11/06
- [PULL 11/49] linux-user/riscv: change default cpu to 'max',
Alistair Francis <=
- [PULL 14/49] qapi,risc-v: add query-cpu-model-expansion, Alistair Francis, 2023/11/06
- [PULL 16/49] target/riscv: handle custom props in qmp_query_cpu_model_expansion, Alistair Francis, 2023/11/06
- [PULL 15/49] target/riscv/tcg: add tcg_cpu_finalize_features(), Alistair Francis, 2023/11/06
- [PULL 17/49] target/riscv: add riscv_cpu_accelerator_compatible(), Alistair Francis, 2023/11/06
- [PULL 20/49] target/riscv: pmp: Clear pmp/smepmp bits on reset, Alistair Francis, 2023/11/06
- [PULL 21/49] target/riscv: pmp: Ignore writes when RW=01, Alistair Francis, 2023/11/06
- [PULL 18/49] target/riscv/riscv-qmp-cmds.c: check CPU accel in query-cpu-model-expansion, Alistair Francis, 2023/11/06
- [PULL 22/49] target/riscv: add zicntr extension flag for TCG, Alistair Francis, 2023/11/06
- [PULL 19/49] Add epmp to extensions list and rename it to smepmp, Alistair Francis, 2023/11/06
- [PULL 23/49] target/riscv/kvm: add zicntr reg, Alistair Francis, 2023/11/06