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[PULL 35/49] target/riscv: Expose Zvkn[c|g] extnesion properties
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From: |
Alistair Francis |
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Subject: |
[PULL 35/49] target/riscv: Expose Zvkn[c|g] extnesion properties |
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Date: |
Tue, 7 Nov 2023 12:29:31 +1000 |
From: Max Chou <max.chou@sifive.com>
Expose the properties of NIST Algorithm Suite related extensions (Zvkn,
Zvknc, Zvkng).
Signed-off-by: Max Chou <max.chou@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20231026151828.754279-8-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 3eedf8b7ce..208faffbbf 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -129,7 +129,10 @@ const RISCVIsaExtData isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(zvfhmin, PRIV_VERSION_1_12_0, ext_zvfhmin),
ISA_EXT_DATA_ENTRY(zvkb, PRIV_VERSION_1_12_0, ext_zvkb),
ISA_EXT_DATA_ENTRY(zvkg, PRIV_VERSION_1_12_0, ext_zvkg),
+ ISA_EXT_DATA_ENTRY(zvkn, PRIV_VERSION_1_12_0, ext_zvkn),
+ ISA_EXT_DATA_ENTRY(zvknc, PRIV_VERSION_1_12_0, ext_zvknc),
ISA_EXT_DATA_ENTRY(zvkned, PRIV_VERSION_1_12_0, ext_zvkned),
+ ISA_EXT_DATA_ENTRY(zvkng, PRIV_VERSION_1_12_0, ext_zvkng),
ISA_EXT_DATA_ENTRY(zvknha, PRIV_VERSION_1_12_0, ext_zvknha),
ISA_EXT_DATA_ENTRY(zvknhb, PRIV_VERSION_1_12_0, ext_zvknhb),
ISA_EXT_DATA_ENTRY(zvksed, PRIV_VERSION_1_12_0, ext_zvksed),
@@ -1394,6 +1397,9 @@ const RISCVCPUMultiExtConfig
riscv_cpu_experimental_exts[] = {
MULTI_EXT_CFG_BOOL("x-zvksed", ext_zvksed, false),
MULTI_EXT_CFG_BOOL("x-zvksh", ext_zvksh, false),
MULTI_EXT_CFG_BOOL("x-zvkt", ext_zvkt, false),
+ MULTI_EXT_CFG_BOOL("x-zvkn", ext_zvkn, false),
+ MULTI_EXT_CFG_BOOL("x-zvknc", ext_zvknc, false),
+ MULTI_EXT_CFG_BOOL("x-zvkng", ext_zvkng, false),
DEFINE_PROP_END_OF_LIST(),
};
--
2.41.0
- [PULL 25/49] target/riscv/kvm: add zihpm reg, (continued)
- [PULL 25/49] target/riscv/kvm: add zihpm reg, Alistair Francis, 2023/11/06
- [PULL 26/49] target/riscv/kvm: add zicsr, zifencei, zba, zbs, svnapot, Alistair Francis, 2023/11/06
- [PULL 27/49] target/riscv: correct csr_ops[CSR_MSECCFG], Alistair Francis, 2023/11/06
- [PULL 28/49] MAINTAINERS: update mail address for Weiwei Li, Alistair Francis, 2023/11/06
- [PULL 31/49] target/riscv: Add cfg property for Zvkb extension, Alistair Francis, 2023/11/06
- [PULL 30/49] target/riscv: Expose Zvkt extension property, Alistair Francis, 2023/11/06
- [PULL 32/49] target/riscv: Replace Zvbb checking by Zvkb, Alistair Francis, 2023/11/06
- [PULL 29/49] target/riscv: Add cfg property for Zvkt extension, Alistair Francis, 2023/11/06
- [PULL 33/49] target/riscv: Expose Zvkb extension property, Alistair Francis, 2023/11/06
- [PULL 34/49] target/riscv: Add cfg properties for Zvkn[c|g] extensions, Alistair Francis, 2023/11/06
- [PULL 35/49] target/riscv: Expose Zvkn[c|g] extnesion properties,
Alistair Francis <=
- [PULL 36/49] target/riscv: Add cfg properties for Zvks[c|g] extensions, Alistair Francis, 2023/11/06
- [PULL 37/49] target/riscv: Expose Zvks[c|g] extnesion properties, Alistair Francis, 2023/11/06
- [PULL 38/49] target/riscv: Move vector crypto extensions to riscv_cpu_extensions, Alistair Francis, 2023/11/06
- [PULL 39/49] disas/riscv: Add rv_fmt_vd_vs2_uimm format, Alistair Francis, 2023/11/06
- [PULL 40/49] disas/riscv: Add rv_codec_vror_vi for vror.vi, Alistair Francis, 2023/11/06
- [PULL 41/49] disas/riscv: Add support for vector crypto extensions, Alistair Francis, 2023/11/06
- [PULL 42/49] disas/riscv: Replace TABs with space, Alistair Francis, 2023/11/06
- [PULL 43/49] hw/ssi: ibex_spi_host: Clear the interrupt even if disabled, Alistair Francis, 2023/11/06
- [PULL 44/49] target/riscv: cpu: Set the OpenTitan priv to 1.12.0, Alistair Francis, 2023/11/06
- [PULL 47/49] target/riscv: Use existing PMU counter mask in FDT generation, Alistair Francis, 2023/11/06