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[PULL 38/49] target/riscv: Move vector crypto extensions to riscv_cpu_ex
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From: |
Alistair Francis |
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Subject: |
[PULL 38/49] target/riscv: Move vector crypto extensions to riscv_cpu_extensions |
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Date: |
Tue, 7 Nov 2023 12:29:34 +1000 |
From: Max Chou <max.chou@sifive.com>
Because the vector crypto specification is ratified, so move theses
extensions from riscv_cpu_experimental_exts to riscv_cpu_extensions.
Signed-off-by: Max Chou <max.chou@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20231026151828.754279-11-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 36 ++++++++++++++++++------------------
1 file changed, 18 insertions(+), 18 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index f61ed7cf60..d73e1da2a2 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1357,6 +1357,24 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
MULTI_EXT_CFG_BOOL("zcmt", ext_zcmt, false),
MULTI_EXT_CFG_BOOL("zicond", ext_zicond, false),
+ /* Vector cryptography extensions */
+ MULTI_EXT_CFG_BOOL("zvbb", ext_zvbb, false),
+ MULTI_EXT_CFG_BOOL("zvbc", ext_zvbc, false),
+ MULTI_EXT_CFG_BOOL("zvkb", ext_zvkg, false),
+ MULTI_EXT_CFG_BOOL("zvkg", ext_zvkg, false),
+ MULTI_EXT_CFG_BOOL("zvkned", ext_zvkned, false),
+ MULTI_EXT_CFG_BOOL("zvknha", ext_zvknha, false),
+ MULTI_EXT_CFG_BOOL("zvknhb", ext_zvknhb, false),
+ MULTI_EXT_CFG_BOOL("zvksed", ext_zvksed, false),
+ MULTI_EXT_CFG_BOOL("zvksh", ext_zvksh, false),
+ MULTI_EXT_CFG_BOOL("zvkt", ext_zvkt, false),
+ MULTI_EXT_CFG_BOOL("zvkn", ext_zvkn, false),
+ MULTI_EXT_CFG_BOOL("zvknc", ext_zvknc, false),
+ MULTI_EXT_CFG_BOOL("zvkng", ext_zvkng, false),
+ MULTI_EXT_CFG_BOOL("zvks", ext_zvks, false),
+ MULTI_EXT_CFG_BOOL("zvksc", ext_zvksc, false),
+ MULTI_EXT_CFG_BOOL("zvksg", ext_zvksg, false),
+
DEFINE_PROP_END_OF_LIST(),
};
@@ -1389,24 +1407,6 @@ const RISCVCPUMultiExtConfig
riscv_cpu_experimental_exts[] = {
MULTI_EXT_CFG_BOOL("x-zvfbfmin", ext_zvfbfmin, false),
MULTI_EXT_CFG_BOOL("x-zvfbfwma", ext_zvfbfwma, false),
- /* Vector cryptography extensions */
- MULTI_EXT_CFG_BOOL("x-zvbb", ext_zvbb, false),
- MULTI_EXT_CFG_BOOL("x-zvbc", ext_zvbc, false),
- MULTI_EXT_CFG_BOOL("x-zvkb", ext_zvkg, false),
- MULTI_EXT_CFG_BOOL("x-zvkg", ext_zvkg, false),
- MULTI_EXT_CFG_BOOL("x-zvkned", ext_zvkned, false),
- MULTI_EXT_CFG_BOOL("x-zvknha", ext_zvknha, false),
- MULTI_EXT_CFG_BOOL("x-zvknhb", ext_zvknhb, false),
- MULTI_EXT_CFG_BOOL("x-zvksed", ext_zvksed, false),
- MULTI_EXT_CFG_BOOL("x-zvksh", ext_zvksh, false),
- MULTI_EXT_CFG_BOOL("x-zvkt", ext_zvkt, false),
- MULTI_EXT_CFG_BOOL("x-zvkn", ext_zvkn, false),
- MULTI_EXT_CFG_BOOL("x-zvknc", ext_zvknc, false),
- MULTI_EXT_CFG_BOOL("x-zvkng", ext_zvkng, false),
- MULTI_EXT_CFG_BOOL("x-zvks", ext_zvks, false),
- MULTI_EXT_CFG_BOOL("x-zvksc", ext_zvksc, false),
- MULTI_EXT_CFG_BOOL("x-zvksg", ext_zvksg, false),
-
DEFINE_PROP_END_OF_LIST(),
};
--
2.41.0
- [PULL 28/49] MAINTAINERS: update mail address for Weiwei Li, (continued)
- [PULL 28/49] MAINTAINERS: update mail address for Weiwei Li, Alistair Francis, 2023/11/06
- [PULL 31/49] target/riscv: Add cfg property for Zvkb extension, Alistair Francis, 2023/11/06
- [PULL 30/49] target/riscv: Expose Zvkt extension property, Alistair Francis, 2023/11/06
- [PULL 32/49] target/riscv: Replace Zvbb checking by Zvkb, Alistair Francis, 2023/11/06
- [PULL 29/49] target/riscv: Add cfg property for Zvkt extension, Alistair Francis, 2023/11/06
- [PULL 33/49] target/riscv: Expose Zvkb extension property, Alistair Francis, 2023/11/06
- [PULL 34/49] target/riscv: Add cfg properties for Zvkn[c|g] extensions, Alistair Francis, 2023/11/06
- [PULL 35/49] target/riscv: Expose Zvkn[c|g] extnesion properties, Alistair Francis, 2023/11/06
- [PULL 36/49] target/riscv: Add cfg properties for Zvks[c|g] extensions, Alistair Francis, 2023/11/06
- [PULL 37/49] target/riscv: Expose Zvks[c|g] extnesion properties, Alistair Francis, 2023/11/06
- [PULL 38/49] target/riscv: Move vector crypto extensions to riscv_cpu_extensions,
Alistair Francis <=
- [PULL 39/49] disas/riscv: Add rv_fmt_vd_vs2_uimm format, Alistair Francis, 2023/11/06
- [PULL 40/49] disas/riscv: Add rv_codec_vror_vi for vror.vi, Alistair Francis, 2023/11/06
- [PULL 41/49] disas/riscv: Add support for vector crypto extensions, Alistair Francis, 2023/11/06
- [PULL 42/49] disas/riscv: Replace TABs with space, Alistair Francis, 2023/11/06
- [PULL 43/49] hw/ssi: ibex_spi_host: Clear the interrupt even if disabled, Alistair Francis, 2023/11/06
- [PULL 44/49] target/riscv: cpu: Set the OpenTitan priv to 1.12.0, Alistair Francis, 2023/11/06
- [PULL 47/49] target/riscv: Use existing PMU counter mask in FDT generation, Alistair Francis, 2023/11/06
- [PULL 45/49] target/riscv: Propagate error from PMU setup, Alistair Francis, 2023/11/06
- [PULL 46/49] target/riscv: Don't assume PMU counters are continuous, Alistair Francis, 2023/11/06