[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 39/49] disas/riscv: Add rv_fmt_vd_vs2_uimm format
|
From: |
Alistair Francis |
|
Subject: |
[PULL 39/49] disas/riscv: Add rv_fmt_vd_vs2_uimm format |
|
Date: |
Tue, 7 Nov 2023 12:29:35 +1000 |
From: Max Chou <max.chou@sifive.com>
Add rv_fmt_vd_vs2_uimm format for vector crypto instructions.
Signed-off-by: Max Chou <max.chou@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231026151828.754279-12-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
disas/riscv.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/disas/riscv.h b/disas/riscv.h
index 8abb578b51..b242d73b25 100644
--- a/disas/riscv.h
+++ b/disas/riscv.h
@@ -274,6 +274,7 @@ enum {
#define rv_fmt_vd_vs2_fs1_vm "O\tD,F,4m"
#define rv_fmt_vd_vs2_imm_vl "O\tD,F,il"
#define rv_fmt_vd_vs2_imm_vm "O\tD,F,im"
+#define rv_fmt_vd_vs2_uimm "O\tD,F,u"
#define rv_fmt_vd_vs2_uimm_vm "O\tD,F,um"
#define rv_fmt_vd_vs1_vs2_vm "O\tD,E,Fm"
#define rv_fmt_vd_rs1_vs2_vm "O\tD,1,Fm"
--
2.41.0
- [PULL 31/49] target/riscv: Add cfg property for Zvkb extension, (continued)
- [PULL 31/49] target/riscv: Add cfg property for Zvkb extension, Alistair Francis, 2023/11/06
- [PULL 30/49] target/riscv: Expose Zvkt extension property, Alistair Francis, 2023/11/06
- [PULL 32/49] target/riscv: Replace Zvbb checking by Zvkb, Alistair Francis, 2023/11/06
- [PULL 29/49] target/riscv: Add cfg property for Zvkt extension, Alistair Francis, 2023/11/06
- [PULL 33/49] target/riscv: Expose Zvkb extension property, Alistair Francis, 2023/11/06
- [PULL 34/49] target/riscv: Add cfg properties for Zvkn[c|g] extensions, Alistair Francis, 2023/11/06
- [PULL 35/49] target/riscv: Expose Zvkn[c|g] extnesion properties, Alistair Francis, 2023/11/06
- [PULL 36/49] target/riscv: Add cfg properties for Zvks[c|g] extensions, Alistair Francis, 2023/11/06
- [PULL 37/49] target/riscv: Expose Zvks[c|g] extnesion properties, Alistair Francis, 2023/11/06
- [PULL 38/49] target/riscv: Move vector crypto extensions to riscv_cpu_extensions, Alistair Francis, 2023/11/06
- [PULL 39/49] disas/riscv: Add rv_fmt_vd_vs2_uimm format,
Alistair Francis <=
- [PULL 40/49] disas/riscv: Add rv_codec_vror_vi for vror.vi, Alistair Francis, 2023/11/06
- [PULL 41/49] disas/riscv: Add support for vector crypto extensions, Alistair Francis, 2023/11/06
- [PULL 42/49] disas/riscv: Replace TABs with space, Alistair Francis, 2023/11/06
- [PULL 43/49] hw/ssi: ibex_spi_host: Clear the interrupt even if disabled, Alistair Francis, 2023/11/06
- [PULL 44/49] target/riscv: cpu: Set the OpenTitan priv to 1.12.0, Alistair Francis, 2023/11/06
- [PULL 47/49] target/riscv: Use existing PMU counter mask in FDT generation, Alistair Francis, 2023/11/06
- [PULL 45/49] target/riscv: Propagate error from PMU setup, Alistair Francis, 2023/11/06
- [PULL 46/49] target/riscv: Don't assume PMU counters are continuous, Alistair Francis, 2023/11/06