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[PULL 42/49] disas/riscv: Replace TABs with space
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From: |
Alistair Francis |
|
Subject: |
[PULL 42/49] disas/riscv: Replace TABs with space |
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Date: |
Tue, 7 Nov 2023 12:29:38 +1000 |
From: Max Chou <max.chou@sifive.com>
Replaces TABs with spaces, making sure to have a consistent coding style
of 4 space indentations.
Signed-off-by: Max Chou <max.chou@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231026151828.754279-15-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
disas/riscv.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/disas/riscv.c b/disas/riscv.c
index 7ea6ea050e..e9458e574b 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -3136,12 +3136,12 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa
isa)
}
break;
case 89:
- switch (((inst >> 12) & 0b111)) {
+ switch (((inst >> 12) & 0b111)) {
case 0: op = rv_op_fmvp_d_x; break;
}
break;
case 91:
- switch (((inst >> 12) & 0b111)) {
+ switch (((inst >> 12) & 0b111)) {
case 0: op = rv_op_fmvp_q_x; break;
}
break;
@@ -4579,7 +4579,7 @@ static void decode_inst_operands(rv_decode *dec, rv_isa
isa)
break;
case rv_codec_zcmt_jt:
dec->imm = operand_tbl_index(inst);
- break;
+ break;
case rv_codec_fli:
dec->rd = operand_rd(inst);
dec->imm = operand_rs1(inst);
--
2.41.0
- [PULL 29/49] target/riscv: Add cfg property for Zvkt extension, (continued)
- [PULL 29/49] target/riscv: Add cfg property for Zvkt extension, Alistair Francis, 2023/11/06
- [PULL 33/49] target/riscv: Expose Zvkb extension property, Alistair Francis, 2023/11/06
- [PULL 34/49] target/riscv: Add cfg properties for Zvkn[c|g] extensions, Alistair Francis, 2023/11/06
- [PULL 35/49] target/riscv: Expose Zvkn[c|g] extnesion properties, Alistair Francis, 2023/11/06
- [PULL 36/49] target/riscv: Add cfg properties for Zvks[c|g] extensions, Alistair Francis, 2023/11/06
- [PULL 37/49] target/riscv: Expose Zvks[c|g] extnesion properties, Alistair Francis, 2023/11/06
- [PULL 38/49] target/riscv: Move vector crypto extensions to riscv_cpu_extensions, Alistair Francis, 2023/11/06
- [PULL 39/49] disas/riscv: Add rv_fmt_vd_vs2_uimm format, Alistair Francis, 2023/11/06
- [PULL 40/49] disas/riscv: Add rv_codec_vror_vi for vror.vi, Alistair Francis, 2023/11/06
- [PULL 41/49] disas/riscv: Add support for vector crypto extensions, Alistair Francis, 2023/11/06
- [PULL 42/49] disas/riscv: Replace TABs with space,
Alistair Francis <=
- [PULL 43/49] hw/ssi: ibex_spi_host: Clear the interrupt even if disabled, Alistair Francis, 2023/11/06
- [PULL 44/49] target/riscv: cpu: Set the OpenTitan priv to 1.12.0, Alistair Francis, 2023/11/06
- [PULL 47/49] target/riscv: Use existing PMU counter mask in FDT generation, Alistair Francis, 2023/11/06
- [PULL 45/49] target/riscv: Propagate error from PMU setup, Alistair Francis, 2023/11/06
- [PULL 46/49] target/riscv: Don't assume PMU counters are continuous, Alistair Francis, 2023/11/06
- [PULL 48/49] target/riscv: Add "pmu-mask" property to replace "pmu-num", Alistair Francis, 2023/11/06
- [PULL 49/49] docs/about/deprecated: Document RISC-V "pmu-num" deprecation, Alistair Francis, 2023/11/06
- Re: [PULL 00/49] riscv-to-apply queue, Stefan Hajnoczi, 2023/11/06