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[PATCH 02/35] tcg: Add C_N2_I1
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From: |
Richard Henderson |
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Subject: |
[PATCH 02/35] tcg: Add C_N2_I1 |
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Date: |
Mon, 6 Nov 2023 18:48:09 -0800 |
Constraint with two outputs, both in new registers.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Jiajie Chen <c@jia.je>
Message-Id: <20230916220151.526140-2-richard.henderson@linaro.org>
---
tcg/tcg.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 847d749a7e..6766b60b8a 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -653,6 +653,7 @@ static void tcg_out_movext3(TCGContext *s, const
TCGMovExtend *i1,
#define C_O1_I4(O1, I1, I2, I3, I4) C_PFX5(c_o1_i4_, O1, I1, I2, I3, I4),
#define C_N1_I2(O1, I1, I2) C_PFX3(c_n1_i2_, O1, I1, I2),
+#define C_N2_I1(O1, O2, I1) C_PFX3(c_n2_i1_, O1, O2, I1),
#define C_O2_I1(O1, O2, I1) C_PFX3(c_o2_i1_, O1, O2, I1),
#define C_O2_I2(O1, O2, I1, I2) C_PFX4(c_o2_i2_, O1, O2, I1, I2),
@@ -675,6 +676,7 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode);
#undef C_O1_I3
#undef C_O1_I4
#undef C_N1_I2
+#undef C_N2_I1
#undef C_O2_I1
#undef C_O2_I2
#undef C_O2_I3
@@ -694,6 +696,7 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode);
#define C_O1_I4(O1, I1, I2, I3, I4) { .args_ct_str = { #O1, #I1, #I2, #I3,
#I4 } },
#define C_N1_I2(O1, I1, I2) { .args_ct_str = { "&" #O1, #I1, #I2 }
},
+#define C_N2_I1(O1, O2, I1) { .args_ct_str = { "&" #O1, "&" #O2,
#I1 } },
#define C_O2_I1(O1, O2, I1) { .args_ct_str = { #O1, #O2, #I1 } },
#define C_O2_I2(O1, O2, I1, I2) { .args_ct_str = { #O1, #O2, #I1, #I2
} },
@@ -715,6 +718,7 @@ static const TCGTargetOpDef constraint_sets[] = {
#undef C_O1_I3
#undef C_O1_I4
#undef C_N1_I2
+#undef C_N2_I1
#undef C_O2_I1
#undef C_O2_I2
#undef C_O2_I3
@@ -734,6 +738,7 @@ static const TCGTargetOpDef constraint_sets[] = {
#define C_O1_I4(O1, I1, I2, I3, I4) C_PFX5(c_o1_i4_, O1, I1, I2, I3, I4)
#define C_N1_I2(O1, I1, I2) C_PFX3(c_n1_i2_, O1, I1, I2)
+#define C_N2_I1(O1, O2, I1) C_PFX3(c_n2_i1_, O1, O2, I1)
#define C_O2_I1(O1, O2, I1) C_PFX3(c_o2_i1_, O1, O2, I1)
#define C_O2_I2(O1, O2, I1, I2) C_PFX4(c_o2_i2_, O1, O2, I1, I2)
--
2.34.1
- [PATCH 00/35] tcg patch queue, Richard Henderson, 2023/11/06
- [PATCH 01/35] accel/tcg: Move HMP info jit and info opcount code, Richard Henderson, 2023/11/06
- [PATCH 03/35] tcg/loongarch64: Use C_N2_I1 for INDEX_op_qemu_ld_a*_i128, Richard Henderson, 2023/11/06
- [PATCH 02/35] tcg: Add C_N2_I1,
Richard Henderson <=
- [PATCH 04/35] util: Add cpuinfo for loongarch64, Richard Henderson, 2023/11/06
- [PATCH 05/35] tcg/loongarch64: Use cpuinfo.h, Richard Henderson, 2023/11/06
- [PATCH 07/35] accel/tcg: Remove redundant case in store_atom_16, Richard Henderson, 2023/11/06
- [PATCH 08/35] accel/tcg: Fix condition for store_atom_insert_al16, Richard Henderson, 2023/11/06
- [PATCH 11/35] tcg: Move generic expanders out of line, Richard Henderson, 2023/11/06
- [PATCH 09/35] tcg: Mark tcg_gen_op* as noinline, Richard Henderson, 2023/11/06
- [PATCH 10/35] tcg: Move tcg_gen_op* out of line, Richard Henderson, 2023/11/06
- [PATCH 12/35] tcg: Move 32-bit expanders out of line, Richard Henderson, 2023/11/06
- [PATCH 15/35] tcg: Move tcg_gen_opN declarations to tcg-internal.h, Richard Henderson, 2023/11/06
- [PATCH 13/35] tcg: Move 64-bit expanders out of line, Richard Henderson, 2023/11/06