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[PATCH 08/35] accel/tcg: Fix condition for store_atom_insert_al16
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From: |
Richard Henderson |
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Subject: |
[PATCH 08/35] accel/tcg: Fix condition for store_atom_insert_al16 |
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Date: |
Mon, 6 Nov 2023 18:48:15 -0800 |
Store bytes under a mask is fundamentally a cmpxchg, not a straight store.
Use HAVE_CMPXCHG128 instead of HAVE_ATOMIC128_RW.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230916220151.526140-8-richard.henderson@linaro.org>
---
accel/tcg/cputlb.c | 2 +-
accel/tcg/ldst_atomicity.c.inc | 10 +++++-----
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index 13986820fe..f35c5f359b 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -2691,7 +2691,7 @@ static uint64_t do_st16_leN(CPUState *cpu,
MMULookupPageData *p,
case MO_ATOM_WITHIN16_PAIR:
/* Since size > 8, this is the half that must be atomic. */
- if (!HAVE_ATOMIC128_RW) {
+ if (!HAVE_CMPXCHG128) {
cpu_loop_exit_atomic(cpu, ra);
}
return store_whole_le16(p->haddr, p->size, val_le);
diff --git a/accel/tcg/ldst_atomicity.c.inc b/accel/tcg/ldst_atomicity.c.inc
index e8f97506fa..33a04dec52 100644
--- a/accel/tcg/ldst_atomicity.c.inc
+++ b/accel/tcg/ldst_atomicity.c.inc
@@ -825,7 +825,7 @@ static uint64_t store_whole_le16(void *pv, int size, Int128
val_le)
int sh = o * 8;
Int128 m, v;
- qemu_build_assert(HAVE_ATOMIC128_RW);
+ qemu_build_assert(HAVE_CMPXCHG128);
/* Like MAKE_64BIT_MASK(0, sz), but larger. */
if (sz <= 64) {
@@ -887,7 +887,7 @@ static void store_atom_2(CPUState *cpu, uintptr_t ra,
return;
}
} else if ((pi & 15) == 7) {
- if (HAVE_ATOMIC128_RW) {
+ if (HAVE_CMPXCHG128) {
Int128 v = int128_lshift(int128_make64(val), 56);
Int128 m = int128_lshift(int128_make64(0xffff), 56);
store_atom_insert_al16(pv - 7, v, m);
@@ -956,7 +956,7 @@ static void store_atom_4(CPUState *cpu, uintptr_t ra,
return;
}
} else {
- if (HAVE_ATOMIC128_RW) {
+ if (HAVE_CMPXCHG128) {
store_whole_le16(pv, 4, int128_make64(cpu_to_le32(val)));
return;
}
@@ -1021,7 +1021,7 @@ static void store_atom_8(CPUState *cpu, uintptr_t ra,
}
break;
case MO_64:
- if (HAVE_ATOMIC128_RW) {
+ if (HAVE_CMPXCHG128) {
store_whole_le16(pv, 8, int128_make64(cpu_to_le64(val)));
return;
}
@@ -1076,7 +1076,7 @@ static void store_atom_16(CPUState *cpu, uintptr_t ra,
}
break;
case -MO_64:
- if (HAVE_ATOMIC128_RW) {
+ if (HAVE_CMPXCHG128) {
uint64_t val_le;
int s2 = pi & 15;
int s1 = 16 - s2;
--
2.34.1
- [PATCH 00/35] tcg patch queue, Richard Henderson, 2023/11/06
- [PATCH 01/35] accel/tcg: Move HMP info jit and info opcount code, Richard Henderson, 2023/11/06
- [PATCH 03/35] tcg/loongarch64: Use C_N2_I1 for INDEX_op_qemu_ld_a*_i128, Richard Henderson, 2023/11/06
- [PATCH 02/35] tcg: Add C_N2_I1, Richard Henderson, 2023/11/06
- [PATCH 04/35] util: Add cpuinfo for loongarch64, Richard Henderson, 2023/11/06
- [PATCH 05/35] tcg/loongarch64: Use cpuinfo.h, Richard Henderson, 2023/11/06
- [PATCH 07/35] accel/tcg: Remove redundant case in store_atom_16, Richard Henderson, 2023/11/06
- [PATCH 08/35] accel/tcg: Fix condition for store_atom_insert_al16,
Richard Henderson <=
- [PATCH 11/35] tcg: Move generic expanders out of line, Richard Henderson, 2023/11/06
- [PATCH 09/35] tcg: Mark tcg_gen_op* as noinline, Richard Henderson, 2023/11/06
- [PATCH 10/35] tcg: Move tcg_gen_op* out of line, Richard Henderson, 2023/11/06
- [PATCH 12/35] tcg: Move 32-bit expanders out of line, Richard Henderson, 2023/11/06
- [PATCH 15/35] tcg: Move tcg_gen_opN declarations to tcg-internal.h, Richard Henderson, 2023/11/06
- [PATCH 13/35] tcg: Move 64-bit expanders out of line, Richard Henderson, 2023/11/06
- [PATCH 14/35] tcg: Move vec_gen_* declarations to tcg-internal.h, Richard Henderson, 2023/11/06
- [PATCH 17/35] tcg: Move tcg_constant_* out of line, Richard Henderson, 2023/11/06
- [PATCH 16/35] tcg: Unexport tcg_gen_op*_{i32,i64}, Richard Henderson, 2023/11/06
- [PATCH 18/35] tcg: Move tcg_temp_new_*, tcg_global_mem_new_* out of line, Richard Henderson, 2023/11/06