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[PULL 28/85] target/hppa: Mask inputs in copy_iaoq_entry
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From: |
Richard Henderson |
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Subject: |
[PULL 28/85] target/hppa: Mask inputs in copy_iaoq_entry |
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Date: |
Mon, 6 Nov 2023 19:03:10 -0800 |
Ensure that the destination is always a valid GVA offset.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/translate.c | 16 ++++++++++++++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index c2db2782f4..cf05d8b6e4 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -720,10 +720,22 @@ static target_ureg gva_offset_mask(DisasContext *ctx)
static void copy_iaoq_entry(DisasContext *ctx, TCGv_reg dest,
target_ureg ival, TCGv_reg vval)
{
- if (unlikely(ival == -1)) {
+ target_ureg mask = gva_offset_mask(ctx);
+
+ if (ival != -1) {
+ tcg_gen_movi_reg(dest, ival & mask);
+ return;
+ }
+ tcg_debug_assert(vval != NULL);
+
+ /*
+ * We know that the IAOQ is already properly masked.
+ * This optimization is primarily for "iaoq_f = iaoq_b".
+ */
+ if (vval == cpu_iaoq_f || vval == cpu_iaoq_b) {
tcg_gen_mov_reg(dest, vval);
} else {
- tcg_gen_movi_reg(dest, ival);
+ tcg_gen_andi_reg(dest, vval, mask);
}
}
--
2.34.1
- [PULL 38/85] target/hppa: Decode d for logical instructions, (continued)
- [PULL 38/85] target/hppa: Decode d for logical instructions, Richard Henderson, 2023/11/06
- [PULL 16/85] target/hppa: Fix extrw and depw with sar for hppa64, Richard Henderson, 2023/11/06
- [PULL 17/85] target/hppa: Introduce TYPE_HPPA64_CPU, Richard Henderson, 2023/11/06
- [PULL 06/85] target/hppa: Populate an interval tree with valid tlb entries, Richard Henderson, 2023/11/06
- [PULL 26/85] target/hppa: Always use copy_iaoq_entry to set cpu_iaoq_[fb], Richard Henderson, 2023/11/06
- [PULL 07/85] target/hppa: Remove get_temp, Richard Henderson, 2023/11/06
- [PULL 09/85] target/hppa: Remove load_const, Richard Henderson, 2023/11/06
- [PULL 25/85] target/hppa: Pass DisasContext to copy_iaoq_entry, Richard Henderson, 2023/11/06
- [PULL 19/85] target/hppa: Implement cpu_list, Richard Henderson, 2023/11/06
- [PULL 27/85] target/hppa: Use copy_iaoq_entry for link in do_ibranch, Richard Henderson, 2023/11/06
- [PULL 28/85] target/hppa: Mask inputs in copy_iaoq_entry,
Richard Henderson <=
- [PULL 29/85] target/hppa: sar register allows only 5 bits on 32-bit CPU, Richard Henderson, 2023/11/06
- [PULL 31/85] target/hppa: Pass d to do_sub_cond, Richard Henderson, 2023/11/06
- [PULL 21/85] target/hppa: Update cpu_hppa_get/put_psw for hppa64, Richard Henderson, 2023/11/06
- [PULL 33/85] target/hppa: Pass d to do_sed_cond, Richard Henderson, 2023/11/06
- [PULL 23/85] target/hppa: Adjust hppa_cpu_dump_state for hppa64, Richard Henderson, 2023/11/06
- [PULL 24/85] target/hppa: Fix hppa64 addressing, Richard Henderson, 2023/11/06
- [PULL 35/85] linux-user/hppa: Fixes for TARGET_ABI32, Richard Henderson, 2023/11/06
- [PULL 34/85] target/hppa: Pass d to do_unit_cond, Richard Henderson, 2023/11/06
- [PULL 39/85] target/hppa: Decode d for unit instructions, Richard Henderson, 2023/11/06
- [PULL 20/85] target/hppa: Implement hppa_cpu_class_by_name, Richard Henderson, 2023/11/06