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[PULL 33/85] target/hppa: Pass d to do_sed_cond
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From: |
Richard Henderson |
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Subject: |
[PULL 33/85] target/hppa: Pass d to do_sed_cond |
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Date: |
Mon, 6 Nov 2023 19:03:15 -0800 |
Hoist the resolution of d up one level above do_sed_cond.
The MOVB comparison and the existing shift/extract/deposit
are all 32-bit.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/translate.c | 24 +++++++++++++-----------
1 file changed, 13 insertions(+), 11 deletions(-)
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index ac7f1f048c..eb4605a9c7 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -1050,10 +1050,10 @@ static DisasCond do_log_cond(DisasContext *ctx,
unsigned cf, bool d,
/* Similar, but for shift/extract/deposit conditions. */
-static DisasCond do_sed_cond(DisasContext *ctx, unsigned orig, TCGv_reg res)
+static DisasCond do_sed_cond(DisasContext *ctx, unsigned orig, bool d,
+ TCGv_reg res)
{
unsigned c, f;
- bool d = false;
/* Convert the compressed condition codes to standard.
0-2 are the same as logicals (nv,<,<=), while 3 is OD.
@@ -3224,7 +3224,8 @@ static bool trans_movb(DisasContext *ctx, arg_movb *a)
tcg_gen_mov_reg(dest, cpu_gr[a->r1]);
}
- cond = do_sed_cond(ctx, a->c, dest);
+ /* All MOVB conditions are 32-bit. */
+ cond = do_sed_cond(ctx, a->c, false, dest);
return do_cbranch(ctx, a->disp, a->n, &cond);
}
@@ -3238,7 +3239,8 @@ static bool trans_movbi(DisasContext *ctx, arg_movbi *a)
dest = dest_gpr(ctx, a->r);
tcg_gen_movi_reg(dest, a->i);
- cond = do_sed_cond(ctx, a->c, dest);
+ /* All MOVBI conditions are 32-bit. */
+ cond = do_sed_cond(ctx, a->c, false, dest);
return do_cbranch(ctx, a->disp, a->n, &cond);
}
@@ -3276,7 +3278,7 @@ static bool trans_shrpw_sar(DisasContext *ctx,
arg_shrpw_sar *a)
/* Install the new nullification. */
cond_free(&ctx->null_cond);
if (a->c) {
- ctx->null_cond = do_sed_cond(ctx, a->c, dest);
+ ctx->null_cond = do_sed_cond(ctx, a->c, false, dest);
}
return nullify_end(ctx);
}
@@ -3312,7 +3314,7 @@ static bool trans_shrpw_imm(DisasContext *ctx,
arg_shrpw_imm *a)
/* Install the new nullification. */
cond_free(&ctx->null_cond);
if (a->c) {
- ctx->null_cond = do_sed_cond(ctx, a->c, dest);
+ ctx->null_cond = do_sed_cond(ctx, a->c, false, dest);
}
return nullify_end(ctx);
}
@@ -3346,7 +3348,7 @@ static bool trans_extrw_sar(DisasContext *ctx,
arg_extrw_sar *a)
/* Install the new nullification. */
cond_free(&ctx->null_cond);
if (a->c) {
- ctx->null_cond = do_sed_cond(ctx, a->c, dest);
+ ctx->null_cond = do_sed_cond(ctx, a->c, false, dest);
}
return nullify_end(ctx);
}
@@ -3373,7 +3375,7 @@ static bool trans_extrw_imm(DisasContext *ctx,
arg_extrw_imm *a)
/* Install the new nullification. */
cond_free(&ctx->null_cond);
if (a->c) {
- ctx->null_cond = do_sed_cond(ctx, a->c, dest);
+ ctx->null_cond = do_sed_cond(ctx, a->c, false, dest);
}
return nullify_end(ctx);
}
@@ -3410,7 +3412,7 @@ static bool trans_depwi_imm(DisasContext *ctx,
arg_depwi_imm *a)
/* Install the new nullification. */
cond_free(&ctx->null_cond);
if (a->c) {
- ctx->null_cond = do_sed_cond(ctx, a->c, dest);
+ ctx->null_cond = do_sed_cond(ctx, a->c, false, dest);
}
return nullify_end(ctx);
}
@@ -3440,7 +3442,7 @@ static bool trans_depw_imm(DisasContext *ctx,
arg_depw_imm *a)
/* Install the new nullification. */
cond_free(&ctx->null_cond);
if (a->c) {
- ctx->null_cond = do_sed_cond(ctx, a->c, dest);
+ ctx->null_cond = do_sed_cond(ctx, a->c, false, dest);
}
return nullify_end(ctx);
}
@@ -3477,7 +3479,7 @@ static bool do_depw_sar(DisasContext *ctx, unsigned rt,
unsigned c,
/* Install the new nullification. */
cond_free(&ctx->null_cond);
if (c) {
- ctx->null_cond = do_sed_cond(ctx, c, dest);
+ ctx->null_cond = do_sed_cond(ctx, c, false, dest);
}
return nullify_end(ctx);
}
--
2.34.1
- [PULL 26/85] target/hppa: Always use copy_iaoq_entry to set cpu_iaoq_[fb], (continued)
- [PULL 26/85] target/hppa: Always use copy_iaoq_entry to set cpu_iaoq_[fb], Richard Henderson, 2023/11/06
- [PULL 07/85] target/hppa: Remove get_temp, Richard Henderson, 2023/11/06
- [PULL 09/85] target/hppa: Remove load_const, Richard Henderson, 2023/11/06
- [PULL 25/85] target/hppa: Pass DisasContext to copy_iaoq_entry, Richard Henderson, 2023/11/06
- [PULL 19/85] target/hppa: Implement cpu_list, Richard Henderson, 2023/11/06
- [PULL 27/85] target/hppa: Use copy_iaoq_entry for link in do_ibranch, Richard Henderson, 2023/11/06
- [PULL 28/85] target/hppa: Mask inputs in copy_iaoq_entry, Richard Henderson, 2023/11/06
- [PULL 29/85] target/hppa: sar register allows only 5 bits on 32-bit CPU, Richard Henderson, 2023/11/06
- [PULL 31/85] target/hppa: Pass d to do_sub_cond, Richard Henderson, 2023/11/06
- [PULL 21/85] target/hppa: Update cpu_hppa_get/put_psw for hppa64, Richard Henderson, 2023/11/06
- [PULL 33/85] target/hppa: Pass d to do_sed_cond,
Richard Henderson <=
- [PULL 23/85] target/hppa: Adjust hppa_cpu_dump_state for hppa64, Richard Henderson, 2023/11/06
- [PULL 24/85] target/hppa: Fix hppa64 addressing, Richard Henderson, 2023/11/06
- [PULL 35/85] linux-user/hppa: Fixes for TARGET_ABI32, Richard Henderson, 2023/11/06
- [PULL 34/85] target/hppa: Pass d to do_unit_cond, Richard Henderson, 2023/11/06
- [PULL 39/85] target/hppa: Decode d for unit instructions, Richard Henderson, 2023/11/06
- [PULL 20/85] target/hppa: Implement hppa_cpu_class_by_name, Richard Henderson, 2023/11/06
- [PULL 32/85] target/hppa: Pass d to do_log_cond, Richard Henderson, 2023/11/06
- [PULL 36/85] target/hppa: Drop attempted gdbstub support for hppa64, Richard Henderson, 2023/11/06
- [PULL 40/85] target/hppa: Decode d for cmpclr instructions, Richard Henderson, 2023/11/06
- [PULL 42/85] target/hppa: Decode d for sub instructions, Richard Henderson, 2023/11/06