[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 67/85] target/hppa: Implement PERMH
|
From: |
Richard Henderson |
|
Subject: |
[PULL 67/85] target/hppa: Implement PERMH |
|
Date: |
Mon, 6 Nov 2023 19:03:49 -0800 |
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/insns.decode | 2 ++
target/hppa/translate.c | 29 +++++++++++++++++++++++++++++
2 files changed, 31 insertions(+)
diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode
index 22ec07f892..19e537df24 100644
--- a/target/hppa/insns.decode
+++ b/target/hppa/insns.decode
@@ -238,6 +238,8 @@ mixh_r 111110 ..... ..... 1 10 00100000 ..... @rrr
mixw_l 111110 ..... ..... 1 00 00000000 ..... @rrr
mixw_r 111110 ..... ..... 1 10 00000000 ..... @rrr
+permh 111110 r1:5 r2:5 0 c0:2 0 c1:2 c2:2 c3:2 0 t:5
+
####
# Index Mem
####
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 2b471444d0..ffdd306d31 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -2946,6 +2946,35 @@ static bool trans_mixw_r(DisasContext *ctx, arg_rrr *a)
return do_multimedia(ctx, a, gen_mixw_r);
}
+static bool trans_permh(DisasContext *ctx, arg_permh *a)
+{
+ TCGv_i64 r, t0, t1, t2, t3;
+
+ if (!ctx->is_pa20) {
+ return false;
+ }
+
+ nullify_over(ctx);
+
+ r = load_gpr(ctx, a->r1);
+ t0 = tcg_temp_new_i64();
+ t1 = tcg_temp_new_i64();
+ t2 = tcg_temp_new_i64();
+ t3 = tcg_temp_new_i64();
+
+ tcg_gen_extract_i64(t0, r, (3 - a->c0) * 16, 16);
+ tcg_gen_extract_i64(t1, r, (3 - a->c1) * 16, 16);
+ tcg_gen_extract_i64(t2, r, (3 - a->c2) * 16, 16);
+ tcg_gen_extract_i64(t3, r, (3 - a->c3) * 16, 16);
+
+ tcg_gen_deposit_i64(t0, t1, t0, 16, 48);
+ tcg_gen_deposit_i64(t2, t3, t2, 16, 48);
+ tcg_gen_deposit_i64(t0, t2, t0, 32, 32);
+
+ save_gpr(ctx, a->t, t0);
+ return nullify_end(ctx);
+}
+
static bool trans_ld(DisasContext *ctx, arg_ldst *a)
{
if (!ctx->is_pa20 && a->size > MO_32) {
--
2.34.1
- [PULL 54/85] hw/hppa: Use uint32_t instead of target_ureg, (continued)
- [PULL 54/85] hw/hppa: Use uint32_t instead of target_ureg, Richard Henderson, 2023/11/06
- [PULL 57/85] target/hppa: Remove remaining TARGET_REGISTER_BITS redirections, Richard Henderson, 2023/11/06
- [PULL 55/85] target/hppa: Remove TARGET_REGISTER_BITS, Richard Henderson, 2023/11/06
- [PULL 45/85] target/hppa: Decode CMPIB double-word, Richard Henderson, 2023/11/06
- [PULL 49/85] target/hppa: Implement EXTRD, Richard Henderson, 2023/11/06
- [PULL 56/85] target/hppa: Remove most of the TARGET_REGISTER_BITS redirections, Richard Henderson, 2023/11/06
- [PULL 60/85] target/hppa: Replace tcg_gen_*_tl with tcg_gen_*_i64, Richard Henderson, 2023/11/06
- [PULL 62/85] target/hppa: Implement HSUB, Richard Henderson, 2023/11/06
- [PULL 58/85] target/hppa: Adjust vmstate_env for pa2.0 tlb, Richard Henderson, 2023/11/06
- [PULL 64/85] target/hppa: Implement HSHL, HSHR, Richard Henderson, 2023/11/06
- [PULL 67/85] target/hppa: Implement PERMH,
Richard Henderson <=
- [PULL 59/85] target/hppa: Use tcg_temp_new_i64 not tcg_temp_new, Richard Henderson, 2023/11/06
- [PULL 74/85] target/hppa: Implement pa2.0 data prefetch instructions, Richard Henderson, 2023/11/06
- [PULL 63/85] target/hppa: Implement HAVG, Richard Henderson, 2023/11/06
- [PULL 70/85] target/hppa: Return zero for r0 from load_gpr, Richard Henderson, 2023/11/06
- [PULL 66/85] target/hppa: Implement MIXH, MIXW, Richard Henderson, 2023/11/06
- [PULL 68/85] target/hppa: Fix interruption based on default PSW, Richard Henderson, 2023/11/06
- [PULL 69/85] target/hppa: Precompute zero into DisasContext, Richard Henderson, 2023/11/06
- [PULL 73/85] linux-user/hppa: Drop EXCP_DUMP from handled exceptions, Richard Henderson, 2023/11/06
- [PULL 72/85] hw/hppa: Translate phys addresses for the cpu, Richard Henderson, 2023/11/06
- [PULL 78/85] target/hppa: Add unwind_breg to CPUHPPAState, Richard Henderson, 2023/11/06