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[PULL 65/85] target/hppa: Implement HSHLADD, HSHRADD
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From: |
Richard Henderson |
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Subject: |
[PULL 65/85] target/hppa: Implement HSHLADD, HSHRADD |
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Date: |
Mon, 6 Nov 2023 19:03:47 -0800 |
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/helper.h | 2 ++
target/hppa/insns.decode | 12 ++++++++++--
target/hppa/op_helper.c | 32 ++++++++++++++++++++++++++++++++
target/hppa/translate.c | 32 ++++++++++++++++++++++++++++++++
4 files changed, 76 insertions(+), 2 deletions(-)
diff --git a/target/hppa/helper.h b/target/hppa/helper.h
index 3b3a543216..d586be3f15 100644
--- a/target/hppa/helper.h
+++ b/target/hppa/helper.h
@@ -17,6 +17,8 @@ DEF_HELPER_FLAGS_1(ldc_check, TCG_CALL_NO_RWG, void, tl)
DEF_HELPER_FLAGS_2(hadd_ss, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(hadd_us, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(havg, TCG_CALL_NO_RWG_SE, i64, i64, i64)
+DEF_HELPER_FLAGS_3(hshladd, TCG_CALL_NO_RWG_SE, i64, i64, i64, i32)
+DEF_HELPER_FLAGS_3(hshradd, TCG_CALL_NO_RWG_SE, i64, i64, i64, i32)
DEF_HELPER_FLAGS_2(hsub_ss, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(hsub_us, TCG_CALL_NO_RWG_SE, i64, i64, i64)
diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode
index bb5cd267b0..87db726d9e 100644
--- a/target/hppa/insns.decode
+++ b/target/hppa/insns.decode
@@ -68,6 +68,7 @@
&rrr t r1 r2
&rrr_cf t r1 r2 cf
&rrr_cf_d t r1 r2 cf d
+&rrr_sh t r1 r2 sh
&rrr_cf_d_sh t r1 r2 cf d sh
&rri t r i
&rri_cf t r i cf
@@ -86,6 +87,7 @@
@rrr ...... r2:5 r1:5 .... ....... t:5 &rrr
@rrr_cf ...... r2:5 r1:5 cf:4 ....... t:5 &rrr_cf
@rrr_cf_d ...... r2:5 r1:5 cf:4 ...... d:1 t:5 &rrr_cf_d
+@rrr_sh ...... r2:5 r1:5 ........ sh:2 . t:5 &rrr_sh
@rrr_cf_d_sh ...... r2:5 r1:5 cf:4 .... sh:2 d:1 t:5 &rrr_cf_d_sh
@rrr_cf_d_sh0 ...... r2:5 r1:5 cf:4 ...... d:1 t:5 &rrr_cf_d_sh sh=0
@rri_cf ...... r:5 t:5 cf:4 . ........... &rri_cf i=%lowsign_11
@@ -187,14 +189,20 @@ dcor_i 000010 ..... 00000 .... 101111 . .....
@rr_cf_d
add 000010 ..... ..... .... 0110.. . ..... @rrr_cf_d_sh
add_l 000010 ..... ..... .... 1010.. . ..... @rrr_cf_d_sh
add_tsv 000010 ..... ..... .... 1110.. . ..... @rrr_cf_d_sh
-add_c 000010 ..... ..... .... 011100 . ..... @rrr_cf_d_sh0
+{
+ add_c 000010 ..... ..... .... 011100 . ..... @rrr_cf_d_sh0
+ hshladd 000010 ..... ..... 0000 0111.. 0 ..... @rrr_sh
+}
add_c_tsv 000010 ..... ..... .... 111100 . ..... @rrr_cf_d_sh0
sub 000010 ..... ..... .... 010000 . ..... @rrr_cf_d
sub_tsv 000010 ..... ..... .... 110000 . ..... @rrr_cf_d
sub_tc 000010 ..... ..... .... 010011 . ..... @rrr_cf_d
sub_tsv_tc 000010 ..... ..... .... 110011 . ..... @rrr_cf_d
-sub_b 000010 ..... ..... .... 010100 . ..... @rrr_cf_d
+{
+ sub_b 000010 ..... ..... .... 010100 . ..... @rrr_cf_d
+ hshradd 000010 ..... ..... 0000 0101.. 0 ..... @rrr_sh
+}
sub_b_tsv 000010 ..... ..... .... 110100 . ..... @rrr_cf_d
ldil 001000 t:5 ..................... i=%assemble_21
diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c
index e76f201472..a0e31c0c25 100644
--- a/target/hppa/op_helper.c
+++ b/target/hppa/op_helper.c
@@ -455,3 +455,35 @@ uint64_t HELPER(hsub_us)(uint64_t r1, uint64_t r2)
}
return ret;
}
+
+uint64_t HELPER(hshladd)(uint64_t r1, uint64_t r2, uint32_t sh)
+{
+ uint64_t ret = 0;
+
+ for (int i = 0; i < 64; i += 16) {
+ int f1 = sextract64(r1, i, 16);
+ int f2 = sextract64(r2, i, 16);
+ int fr = (f1 << sh) + f2;
+
+ fr = MIN(fr, INT16_MAX);
+ fr = MAX(fr, INT16_MIN);
+ ret = deposit64(ret, i, 16, fr);
+ }
+ return ret;
+}
+
+uint64_t HELPER(hshradd)(uint64_t r1, uint64_t r2, uint32_t sh)
+{
+ uint64_t ret = 0;
+
+ for (int i = 0; i < 64; i += 16) {
+ int f1 = sextract64(r1, i, 16);
+ int f2 = sextract64(r2, i, 16);
+ int fr = (f1 >> sh) + f2;
+
+ fr = MIN(fr, INT16_MAX);
+ fr = MAX(fr, INT16_MIN);
+ ret = deposit64(ret, i, 16, fr);
+ }
+ return ret;
+}
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index a3a12d63f8..648c37fb28 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -2809,6 +2809,28 @@ static bool do_multimedia_sh(DisasContext *ctx, arg_rri
*a,
return nullify_end(ctx);
}
+static bool do_multimedia_shadd(DisasContext *ctx, arg_rrr_sh *a,
+ void (*fn)(TCGv_i64, TCGv_i64,
+ TCGv_i64, TCGv_i32))
+{
+ TCGv_i64 r1, r2, dest;
+
+ if (!ctx->is_pa20) {
+ return false;
+ }
+
+ nullify_over(ctx);
+
+ r1 = load_gpr(ctx, a->r1);
+ r2 = load_gpr(ctx, a->r2);
+ dest = dest_gpr(ctx, a->t);
+
+ fn(dest, r1, r2, tcg_constant_i32(a->sh));
+ save_gpr(ctx, a->t, dest);
+
+ return nullify_end(ctx);
+}
+
static bool trans_hadd(DisasContext *ctx, arg_rrr *a)
{
return do_multimedia(ctx, a, tcg_gen_vec_add16_i64);
@@ -2844,6 +2866,16 @@ static bool trans_hshr_u(DisasContext *ctx, arg_rri *a)
return do_multimedia_sh(ctx, a, tcg_gen_vec_shr16i_i64);
}
+static bool trans_hshladd(DisasContext *ctx, arg_rrr_sh *a)
+{
+ return do_multimedia_shadd(ctx, a, gen_helper_hshladd);
+}
+
+static bool trans_hshradd(DisasContext *ctx, arg_rrr_sh *a)
+{
+ return do_multimedia_shadd(ctx, a, gen_helper_hshradd);
+}
+
static bool trans_hsub(DisasContext *ctx, arg_rrr *a)
{
return do_multimedia(ctx, a, tcg_gen_vec_sub16_i64);
--
2.34.1
- [PULL 66/85] target/hppa: Implement MIXH, MIXW, (continued)
- [PULL 66/85] target/hppa: Implement MIXH, MIXW, Richard Henderson, 2023/11/06
- [PULL 68/85] target/hppa: Fix interruption based on default PSW, Richard Henderson, 2023/11/06
- [PULL 69/85] target/hppa: Precompute zero into DisasContext, Richard Henderson, 2023/11/06
- [PULL 73/85] linux-user/hppa: Drop EXCP_DUMP from handled exceptions, Richard Henderson, 2023/11/06
- [PULL 72/85] hw/hppa: Translate phys addresses for the cpu, Richard Henderson, 2023/11/06
- [PULL 78/85] target/hppa: Add unwind_breg to CPUHPPAState, Richard Henderson, 2023/11/06
- [PULL 77/85] target/hppa: Clear upper bits in mtctl for pa1.x, Richard Henderson, 2023/11/06
- [PULL 75/85] target/hppa: Add pa2.0 cpu local tlb flushes, Richard Henderson, 2023/11/06
- [PULL 71/85] include/hw/elf: Remove truncating signed casts, Richard Henderson, 2023/11/06
- [PULL 65/85] target/hppa: Implement HSHLADD, HSHRADD,
Richard Henderson <=
- [PULL 61/85] target/hppa: Implement HADD, Richard Henderson, 2023/11/06
- [PULL 76/85] target/hppa: Avoid async_safe_run_on_cpu on uniprocessor system, Richard Henderson, 2023/11/06
- [PULL 79/85] target/hppa: Create raise_exception_with_ior, Richard Henderson, 2023/11/06
- [PULL 82/85] hw/pci-host/astro: Map Astro chip into 64-bit I/O memory region, Richard Henderson, 2023/11/06
- [PULL 84/85] hw/hppa: Turn on 64-bit CPU for C3700 machine, Richard Henderson, 2023/11/06
- [PULL 85/85] hw/hppa: Allow C3700 with 64-bit and B160L with 32-bit CPU only, Richard Henderson, 2023/11/06
- [PULL 81/85] target/hppa: Improve interrupt logging, Richard Henderson, 2023/11/06
- [PULL 80/85] target/hppa: Update IIAOQ, IIASQ for pa2.0, Richard Henderson, 2023/11/06
- [PULL 83/85] hw/pci-host/astro: Trigger CPU irq on CPU HPA in high memory, Richard Henderson, 2023/11/06
- Re: [PULL 00/85] target/hppa patch queue, Stefan Hajnoczi, 2023/11/07