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Re: [PULL 46/49] target/riscv: Don't assume PMU counters are continuous
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From: |
Peter Maydell |
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Subject: |
Re: [PULL 46/49] target/riscv: Don't assume PMU counters are continuous |
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Date: |
Thu, 9 Nov 2023 15:24:06 +0000 |
On Tue, 7 Nov 2023 at 02:36, Alistair Francis <alistair23@gmail.com> wrote:
>
> From: Rob Bradford <rbradford@rivosinc.com>
>
> Check the PMU available bitmask when checking if a counter is valid
> rather than comparing the index against the number of PMUs.
>
> Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> Reviewed-by: Atish Patra <atishp@rivosinc.com>
> Message-ID: <20231031154000.18134-3-rbradford@rivosinc.com>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> target/riscv/csr.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index fc26b52c88..fde7ce1a53 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -188,7 +188,8 @@ static RISCVException zcmt(CPURISCVState *env, int csrno)
> #if !defined(CONFIG_USER_ONLY)
> static RISCVException mctr(CPURISCVState *env, int csrno)
> {
> - int pmu_num = riscv_cpu_cfg(env)->pmu_num;
> + RISCVCPU *cpu = env_archcpu(env);
> + uint32_t pmu_avail_ctrs = cpu->pmu_avail_ctrs;
> int ctr_index;
> int base_csrno = CSR_MHPMCOUNTER3;
>
> @@ -197,7 +198,7 @@ static RISCVException mctr(CPURISCVState *env, int csrno)
> base_csrno += 0x80;
> }
> ctr_index = csrno - base_csrno;
> - if (!pmu_num || ctr_index >= pmu_num) {
> + if ((BIT(ctr_index) & pmu_avail_ctrs >> 3) == 0) {
> /* The PMU is not enabled or counter is out of range */
> return RISCV_EXCP_ILLEGAL_INST;
> }
Hi; Coverity is not convinced that ctr_index is necessarily
guaranteed to be within the valid range to be an argument
to BIT() (eg that it won't be negative). Looking at the
code as a human I'm pretty unsure too. Could somebody have
a look at this and maybe improve the readability / add an
assertion / fix a bug if any ? (CID 1523910)
More generally there are about half a dozen other riscv
issues in Coverity at the moment, so if somebody who knows
the riscv code could have a look at them that would be great.
thanks
-- PMM
- [PULL 38/49] target/riscv: Move vector crypto extensions to riscv_cpu_extensions, (continued)
- [PULL 38/49] target/riscv: Move vector crypto extensions to riscv_cpu_extensions, Alistair Francis, 2023/11/06
- [PULL 39/49] disas/riscv: Add rv_fmt_vd_vs2_uimm format, Alistair Francis, 2023/11/06
- [PULL 40/49] disas/riscv: Add rv_codec_vror_vi for vror.vi, Alistair Francis, 2023/11/06
- [PULL 41/49] disas/riscv: Add support for vector crypto extensions, Alistair Francis, 2023/11/06
- [PULL 42/49] disas/riscv: Replace TABs with space, Alistair Francis, 2023/11/06
- [PULL 43/49] hw/ssi: ibex_spi_host: Clear the interrupt even if disabled, Alistair Francis, 2023/11/06
- [PULL 44/49] target/riscv: cpu: Set the OpenTitan priv to 1.12.0, Alistair Francis, 2023/11/06
- [PULL 47/49] target/riscv: Use existing PMU counter mask in FDT generation, Alistair Francis, 2023/11/06
- [PULL 45/49] target/riscv: Propagate error from PMU setup, Alistair Francis, 2023/11/06
- [PULL 46/49] target/riscv: Don't assume PMU counters are continuous, Alistair Francis, 2023/11/06
- Re: [PULL 46/49] target/riscv: Don't assume PMU counters are continuous,
Peter Maydell <=
- [PULL 48/49] target/riscv: Add "pmu-mask" property to replace "pmu-num", Alistair Francis, 2023/11/06
- [PULL 49/49] docs/about/deprecated: Document RISC-V "pmu-num" deprecation, Alistair Francis, 2023/11/06
- Re: [PULL 00/49] riscv-to-apply queue, Stefan Hajnoczi, 2023/11/06