[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 1/4] hw/arm/virt: fix GIC maintenance IRQ registration
|
From: |
Peter Maydell |
|
Subject: |
[PULL 1/4] hw/arm/virt: fix GIC maintenance IRQ registration |
|
Date: |
Mon, 13 Nov 2023 17:46:32 +0000 |
From: Jean-Philippe Brucker <jean-philippe@linaro.org>
Since commit 9036e917f8 ("{include/}hw/arm: refactor virt PPI logic"),
GIC maintenance IRQ registration fails on arm64:
[ 0.979743] kvm [1]: Cannot register interrupt 9
That commit re-defined VIRTUAL_PMU_IRQ to be a INTID but missed a case
where the maintenance IRQ is actually referred by its PPI index. Just
like commit fa68ecb330db ("hw/arm/virt: fix PMU IRQ registration"), use
INITID_TO_PPI(). A search of "GIC_FDT_IRQ_TYPE_PPI" indicates that there
shouldn't be more similar issues.
Fixes: 9036e917f8 ("{include/}hw/arm: refactor virt PPI logic")
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Message-id: 20231110090557.3219206-2-jean-philippe@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/virt.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 85e3c5ba9d2..be2856c018a 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -576,7 +576,8 @@ static void fdt_add_gic_node(VirtMachineState *vms)
if (vms->virt) {
qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
- GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IRQ,
+ GIC_FDT_IRQ_TYPE_PPI,
+ INTID_TO_PPI(ARCH_GIC_MAINT_IRQ),
GIC_FDT_IRQ_FLAGS_LEVEL_HI);
}
} else {
@@ -600,7 +601,8 @@ static void fdt_add_gic_node(VirtMachineState *vms)
2, vms->memmap[VIRT_GIC_VCPU].base,
2, vms->memmap[VIRT_GIC_VCPU].size);
qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
- GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IRQ,
+ GIC_FDT_IRQ_TYPE_PPI,
+ INTID_TO_PPI(ARCH_GIC_MAINT_IRQ),
GIC_FDT_IRQ_FLAGS_LEVEL_HI);
}
}
--
2.34.1
- [PULL 0/4] target-arm queue, Peter Maydell, 2023/11/13
- [PULL 1/4] hw/arm/virt: fix GIC maintenance IRQ registration,
Peter Maydell <=
- [PULL 4/4] target/arm/tcg: enable PMU feature for Cortex-A8 and A9, Peter Maydell, 2023/11/13
- [PULL 3/4] target/arm: Correct MTE tag checking for reverse-copy MOPS, Peter Maydell, 2023/11/13
- [PULL 2/4] target/arm: HVC at EL3 should go to EL3, not EL2, Peter Maydell, 2023/11/13
- Re: [PULL 0/4] target-arm queue, Stefan Hajnoczi, 2023/11/14