Re: [PATCH v5 3/3] hw/ppc: Nest1 chiplet wiring

[Nicholas Piggin]

On Fri Nov 24, 2023 at 10:26 PM AEST, Cédric Le Goater wrote:
> On 11/24/23 12:28, Nicholas Piggin wrote:
> > On Fri Nov 24, 2023 at 8:15 PM AEST, Chalapathi V wrote:
> >> This part of the patchset connects the nest1 chiplet model to p10 chip.
> > 
> > Seems fine to me. Should it just be squashed into patch 2?
>
> It is better to keep the model a part from the wiring because the
> same model could be plugged in different board/machine. It clarifies
> the interfaces, which should be limited to irq connects and memory
> mappings and it makes modeling shortcuts more visible: backpointers,
> looping on the machine mappings to find a core, etc.

Okay that makes sense.

> I didn't comment on the PnvChiptod proposal but it could/should
> be done the same.

I'll look at splitting it too then.

Thanks,
Nick