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[PULL 07/65] target/riscv/kvm: change KVM_REG_RISCV_FP_F to u32
From: |
Alistair Francis |
Subject: |
[PULL 07/65] target/riscv/kvm: change KVM_REG_RISCV_FP_F to u32 |
Date: |
Wed, 10 Jan 2024 18:56:35 +1000 |
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
KVM_REG_RISCV_FP_F regs have u32 size according to the API, but by using
kvm_riscv_reg_id() in RISCV_FP_F_REG() we're returning u64 sizes when
running with TARGET_RISCV64. The most likely reason why no one noticed
this is because we're not implementing kvm_cpu_synchronize_state() in
RISC-V yet.
Create a new helper that returns a KVM ID with u32 size and use it in
RISCV_FP_F_REG().
Reported-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20231208183835.2411523-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/kvm/kvm-cpu.c | 11 ++++++++---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
index 117e33cf90..375c8e7f33 100644
--- a/target/riscv/kvm/kvm-cpu.c
+++ b/target/riscv/kvm/kvm-cpu.c
@@ -72,6 +72,11 @@ static uint64_t kvm_riscv_reg_id(CPURISCVState *env,
uint64_t type,
return id;
}
+static uint64_t kvm_riscv_reg_id_u32(uint64_t type, uint64_t idx)
+{
+ return KVM_REG_RISCV | KVM_REG_SIZE_U32 | type | idx;
+}
+
#define RISCV_CORE_REG(env, name) kvm_riscv_reg_id(env, KVM_REG_RISCV_CORE, \
KVM_REG_RISCV_CORE_REG(name))
@@ -81,7 +86,7 @@ static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t
type,
#define RISCV_TIMER_REG(env, name) kvm_riscv_reg_id(env, KVM_REG_RISCV_TIMER,
\
KVM_REG_RISCV_TIMER_REG(name))
-#define RISCV_FP_F_REG(env, idx) kvm_riscv_reg_id(env, KVM_REG_RISCV_FP_F,
idx)
+#define RISCV_FP_F_REG(idx) kvm_riscv_reg_id_u32(KVM_REG_RISCV_FP_F, idx)
#define RISCV_FP_D_REG(env, idx) kvm_riscv_reg_id(env, KVM_REG_RISCV_FP_D,
idx)
@@ -586,7 +591,7 @@ static int kvm_riscv_get_regs_fp(CPUState *cs)
if (riscv_has_ext(env, RVF)) {
uint32_t reg;
for (i = 0; i < 32; i++) {
- ret = kvm_get_one_reg(cs, RISCV_FP_F_REG(env, i), ®);
+ ret = kvm_get_one_reg(cs, RISCV_FP_F_REG(i), ®);
if (ret) {
return ret;
}
@@ -620,7 +625,7 @@ static int kvm_riscv_put_regs_fp(CPUState *cs)
uint32_t reg;
for (i = 0; i < 32; i++) {
reg = env->fpr[i];
- ret = kvm_set_one_reg(cs, RISCV_FP_F_REG(env, i), ®);
+ ret = kvm_set_one_reg(cs, RISCV_FP_F_REG(i), ®);
if (ret) {
return ret;
}
--
2.43.0
- [PULL 00/65] riscv-to-apply queue, Alistair Francis, 2024/01/10
- [PULL 01/65] target/riscv: Add vill check for whole vector register move instructions, Alistair Francis, 2024/01/10
- [PULL 03/65] target/riscv: Fix th.dcache.cval1 priviledge check, Alistair Francis, 2024/01/10
- [PULL 02/65] target/riscv: The whole vector register move instructions depend on vsew, Alistair Francis, 2024/01/10
- [PULL 04/65] target/riscv: Not allow write mstatus_vs without RVV, Alistair Francis, 2024/01/10
- [PULL 05/65] target/riscv/pmp: Use hwaddr instead of target_ulong for RV32, Alistair Francis, 2024/01/10
- [PULL 06/65] target/riscv/cpu.c: fix machine IDs getters, Alistair Francis, 2024/01/10
- [PULL 07/65] target/riscv/kvm: change KVM_REG_RISCV_FP_F to u32,
Alistair Francis <=
- [PULL 08/65] target/riscv/kvm: change KVM_REG_RISCV_FP_D to u64, Alistair Francis, 2024/01/10
- [PULL 09/65] target/riscv/kvm: change timer regs size to u64, Alistair Francis, 2024/01/10
- [PULL 11/65] target/riscv/kvm: rename riscv_reg_id() to riscv_reg_id_ulong(), Alistair Francis, 2024/01/10
- [PULL 12/65] hw/arm/virt-acpi-build.c: Migrate fw_cfg creation to common location, Alistair Francis, 2024/01/10
- [PULL 13/65] hw/arm/virt-acpi-build.c: Migrate virtio creation to common location, Alistair Francis, 2024/01/10
- [PULL 10/65] target/riscv/kvm: add RISCV_CONFIG_REG(), Alistair Francis, 2024/01/10
- [PULL 14/65] hw/i386/acpi-microvm.c: Use common function to add virtio in DSDT, Alistair Francis, 2024/01/10
- [PULL 15/65] hw/riscv: virt: Make few IMSIC macros and functions public, Alistair Francis, 2024/01/10
- [PULL 16/65] hw/riscv/virt-acpi-build.c: Add AIA support in RINTC, Alistair Francis, 2024/01/10
- [PULL 17/65] hw/riscv/virt-acpi-build.c: Add IMSIC in the MADT, Alistair Francis, 2024/01/10