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[PULL 54/65] target/riscv: add rva22s64 cpu
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From: |
Alistair Francis |
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Subject: |
[PULL 54/65] target/riscv: add rva22s64 cpu |
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Date: |
Wed, 10 Jan 2024 18:57:22 +1000 |
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Add a new profile CPU 'rva22s64' to work as an alias of
-cpu rv64i,rva22s64
Like the existing rva22u64 CPU already does with the RVA22U64 profile.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231218125334.37184-27-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu-qom.h | 1 +
target/riscv/cpu.c | 8 ++++++++
2 files changed, 9 insertions(+)
diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
index 12fe78fc52..9219c2fcc3 100644
--- a/target/riscv/cpu-qom.h
+++ b/target/riscv/cpu-qom.h
@@ -36,6 +36,7 @@
#define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("x-rv128")
#define TYPE_RISCV_CPU_RV64I RISCV_CPU_TYPE_NAME("rv64i")
#define TYPE_RISCV_CPU_RVA22U64 RISCV_CPU_TYPE_NAME("rva22u64")
+#define TYPE_RISCV_CPU_RVA22S64 RISCV_CPU_TYPE_NAME("rva22s64")
#define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex")
#define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c")
#define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31")
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index a8f4081922..b32681f7f3 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1623,6 +1623,13 @@ static void rva22u64_profile_cpu_init(Object *obj)
RVA22U64.enabled = true;
}
+
+static void rva22s64_profile_cpu_init(Object *obj)
+{
+ rv64i_bare_cpu_init(obj);
+
+ RVA22S64.enabled = true;
+}
#endif
static const gchar *riscv_gdb_arch_name(CPUState *cs)
@@ -1938,6 +1945,7 @@ static const TypeInfo riscv_cpu_type_infos[] = {
DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init),
DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV64I, rv64i_bare_cpu_init),
DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22U64, rva22u64_profile_cpu_init),
+ DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22S64, rva22s64_profile_cpu_init),
#endif
};
--
2.43.0
- [PULL 44/65] target/riscv/tcg: validate profiles during finalize, (continued)
- [PULL 44/65] target/riscv/tcg: validate profiles during finalize, Alistair Francis, 2024/01/10
- [PULL 45/65] riscv-qmp-cmds.c: add profile flags in cpu-model-expansion, Alistair Francis, 2024/01/10
- [PULL 46/65] target/riscv: add 'rva22u64' CPU, Alistair Francis, 2024/01/10
- [PULL 47/65] target/riscv: implement svade, Alistair Francis, 2024/01/10
- [PULL 48/65] target/riscv: add priv ver restriction to profiles, Alistair Francis, 2024/01/10
- [PULL 49/65] target/riscv/cpu.c: finalize satp_mode earlier, Alistair Francis, 2024/01/10
- [PULL 50/65] target/riscv/cpu.c: add riscv_cpu_is_32bit(), Alistair Francis, 2024/01/10
- [PULL 51/65] target/riscv: add satp_mode profile support, Alistair Francis, 2024/01/10
- [PULL 52/65] target/riscv: add 'parent' in profile description, Alistair Francis, 2024/01/10
- [PULL 53/65] target/riscv: add RVA22S64 profile, Alistair Francis, 2024/01/10
- [PULL 54/65] target/riscv: add rva22s64 cpu,
Alistair Francis <=
- [PULL 55/65] target/riscv/kvm.c: remove group setting of KVM AIA if the machine only has 1 socket, Alistair Francis, 2024/01/10
- [PULL 56/65] linux-headers: Update to Linux v6.7-rc5, Alistair Francis, 2024/01/10
- [PULL 57/65] linux-headers: riscv: add ptrace.h, Alistair Francis, 2024/01/10
- [PULL 63/65] target/riscv: Assert that the CSR numbers will be correct, Alistair Francis, 2024/01/10
- [PULL 61/65] roms/opensbi: Upgrade from v1.3.1 to v1.4, Alistair Francis, 2024/01/10
- [PULL 62/65] target/riscv: pmp: Ignore writes when RW=01 and MML=0, Alistair Francis, 2024/01/10
- [PULL 58/65] target/riscv/kvm: do PR_RISCV_V_SET_CONTROL during realize(), Alistair Francis, 2024/01/10
- [PULL 59/65] target/riscv/kvm: add RVV and Vector CSR regs, Alistair Francis, 2024/01/10
- [PULL 60/65] docs/system/riscv: sifive_u: Update S-mode U-Boot image build instructions, Alistair Francis, 2024/01/10
- [PULL 65/65] target/riscv: Ensure mideleg is set correctly on reset, Alistair Francis, 2024/01/10