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[PULL 60/65] docs/system/riscv: sifive_u: Update S-mode U-Boot image bui
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From: |
Alistair Francis |
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Subject: |
[PULL 60/65] docs/system/riscv: sifive_u: Update S-mode U-Boot image build instructions |
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Date: |
Wed, 10 Jan 2024 18:57:28 +1000 |
From: Bin Meng <bmeng@tinylab.org>
Currently, the documentation outlines the process for building the
S-mode U-Boot image using `make menuconfig` and manual actions within
the menuconfig UI. However, this approach is fragile due to Kconfig
options potentially changing across different releases. For example,
CONFIG_OF_PRIOR_STAGE has been replaced by CONFIG_BOARD since v2022.01
release, and CONFIG_TEXT_BASE has been moved to the 'General setup'
menu from the 'Boot options' menu in v2024.01 release.
This update aims to make the S-mode U-Boot image build instructions
future-proof. It leverages the 'config' script provided in the U-Boot
source tree to edit the .config file, followed by a `make olddefconfig`.
Validated with U-Boot v2024.01 release.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240104071523.273702-1-bmeng@tinylab.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
docs/system/riscv/sifive_u.rst | 33 ++++++++++++---------------------
1 file changed, 12 insertions(+), 21 deletions(-)
diff --git a/docs/system/riscv/sifive_u.rst b/docs/system/riscv/sifive_u.rst
index 7b166567f9..8f55ae8e31 100644
--- a/docs/system/riscv/sifive_u.rst
+++ b/docs/system/riscv/sifive_u.rst
@@ -210,7 +210,7 @@ command line options with ``qemu-system-riscv32``.
Running U-Boot
--------------
-U-Boot mainline v2021.07 release is tested at the time of writing. To build a
+U-Boot mainline v2024.01 release is tested at the time of writing. To build a
U-Boot mainline bootloader that can be booted by the ``sifive_u`` machine, use
the sifive_unleashed_defconfig with similar commands as described above for
Linux:
@@ -325,15 +325,10 @@ configuration of U-Boot:
$ export CROSS_COMPILE=riscv64-linux-
$ make sifive_unleashed_defconfig
- $ make menuconfig
-
-then manually select the following configuration:
-
- * Device Tree Control ---> Provider of DTB for DT Control ---> Prior Stage
bootloader DTB
-
-and unselect the following configuration:
-
- * Library routines ---> Allow access to binman information in the device tree
+ $ ./scripts/config --enable OF_BOARD
+ $ ./scripts/config --disable BINMAN_FDT
+ $ ./scripts/config --disable SPL
+ $ make olddefconfig
This changes U-Boot to use the QEMU generated device tree blob, and bypass
running the U-Boot SPL stage.
@@ -352,17 +347,13 @@ It's possible to create a 32-bit U-Boot S-mode image as
well.
$ export CROSS_COMPILE=riscv64-linux-
$ make sifive_unleashed_defconfig
- $ make menuconfig
-
-then manually update the following configuration in U-Boot:
-
- * Device Tree Control ---> Provider of DTB for DT Control ---> Prior Stage
bootloader DTB
- * RISC-V architecture ---> Base ISA ---> RV32I
- * Boot options ---> Boot images ---> Text Base ---> 0x80400000
-
-and unselect the following configuration:
-
- * Library routines ---> Allow access to binman information in the device tree
+ $ ./scripts/config --disable ARCH_RV64I
+ $ ./scripts/config --enable ARCH_RV32I
+ $ ./scripts/config --set-val TEXT_BASE 0x80400000
+ $ ./scripts/config --enable OF_BOARD
+ $ ./scripts/config --disable BINMAN_FDT
+ $ ./scripts/config --disable SPL
+ $ make olddefconfig
Use the same command line options to boot the 32-bit U-Boot S-mode image:
--
2.43.0
- [PULL 53/65] target/riscv: add RVA22S64 profile, (continued)
- [PULL 53/65] target/riscv: add RVA22S64 profile, Alistair Francis, 2024/01/10
- [PULL 54/65] target/riscv: add rva22s64 cpu, Alistair Francis, 2024/01/10
- [PULL 55/65] target/riscv/kvm.c: remove group setting of KVM AIA if the machine only has 1 socket, Alistair Francis, 2024/01/10
- [PULL 56/65] linux-headers: Update to Linux v6.7-rc5, Alistair Francis, 2024/01/10
- [PULL 57/65] linux-headers: riscv: add ptrace.h, Alistair Francis, 2024/01/10
- [PULL 63/65] target/riscv: Assert that the CSR numbers will be correct, Alistair Francis, 2024/01/10
- [PULL 61/65] roms/opensbi: Upgrade from v1.3.1 to v1.4, Alistair Francis, 2024/01/10
- [PULL 62/65] target/riscv: pmp: Ignore writes when RW=01 and MML=0, Alistair Francis, 2024/01/10
- [PULL 58/65] target/riscv/kvm: do PR_RISCV_V_SET_CONTROL during realize(), Alistair Francis, 2024/01/10
- [PULL 59/65] target/riscv/kvm: add RVV and Vector CSR regs, Alistair Francis, 2024/01/10
- [PULL 60/65] docs/system/riscv: sifive_u: Update S-mode U-Boot image build instructions,
Alistair Francis <=
- [PULL 65/65] target/riscv: Ensure mideleg is set correctly on reset, Alistair Francis, 2024/01/10
- [PULL 64/65] target/riscv: Don't adjust vscause for exceptions, Alistair Francis, 2024/01/10
- Re: [PULL 00/65] riscv-to-apply queue, Peter Maydell, 2024/01/10