Re: [PULL 00/65] riscv-to-apply queue

[Peter Maydell]

On Wed, 10 Jan 2024 at 08:58, Alistair Francis <alistair23@gmail.com> wrote:
>
> The following changes since commit 9468484fe904ab4691de6d9c34616667f377ceac:
>
>   Merge tag 'block-pull-request' of https://gitlab.com/stefanha/qemu into 
> staging (2024-01-09 10:32:23 +0000)
>
> are available in the Git repository at:
>
>   https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20240110
>
> for you to fetch changes up to 71b76da33a1558bcd59100188f5753737ef6fa21:
>
>   target/riscv: Ensure mideleg is set correctly on reset (2024-01-10 18:47:47 
> +1000)
>
> ----------------------------------------------------------------
> RISC-V PR for 9.0
>
> * Make vector whole-register move (vmv) depend on vtype register
> * Fix th.dcache.cval1 priviledge check
> * Don't allow write mstatus_vs without RVV
> * Use hwaddr instead of target_ulong for RV32
> * Fix machine IDs QOM getters\
> * Fix KVM reg id sizes
> * ACPI: Enable AIA, PLIC and update RHCT
> * Fix the interrupts-extended property format of PLIC
> * Add support for Zacas extension
> * Add amocas.[w,d,q] instructions
> * Document acpi parameter of virt machine
> * RVA22 profiles support
> * Remove group setting of KVM AIA if the machine only has 1 socket
> * Add RVV CSRs to KVM
> * sifive_u: Update S-mode U-Boot image build instructions
> * Upgrade OpenSBI from v1.3.1 to v1.4
> * pmp: Ignore writes when RW=01 and MML=0
> * Assert that the CSR numbers will be correct
> * Don't adjust vscause for exceptions
> * Ensure mideleg is set correctly on reset
>


Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/9.0
for any user-visible changes.

-- PMM