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[PULL 25/41] target/arm: Treat LDTR* and STTR* as LDR/STR when NV, NV1 i
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From: |
Peter Maydell |
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Subject: |
[PULL 25/41] target/arm: Treat LDTR* and STTR* as LDR/STR when NV, NV1 is 1, 1 |
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Date: |
Thu, 11 Jan 2024 11:04:49 +0000 |
FEAT_NV requires (per I_JKLJK) that when HCR_EL2.{NV,NV1} is {1,1} the
unprivileged-access instructions LDTR, STTR etc behave as normal
loads and stores. Implement the check that handles this.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Miguel Luis <miguel.luis@oracle.com>
---
target/arm/tcg/hflags.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/target/arm/tcg/hflags.c b/target/arm/tcg/hflags.c
index f33c0a12741..8f254bf9ccb 100644
--- a/target/arm/tcg/hflags.c
+++ b/target/arm/tcg/hflags.c
@@ -261,8 +261,10 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env,
int el, int fp_el,
switch (mmu_idx) {
case ARMMMUIdx_E10_1:
case ARMMMUIdx_E10_1_PAN:
- /* TODO: ARMv8.3-NV */
- DP_TBFLAG_A64(flags, UNPRIV, 1);
+ /* FEAT_NV: NV,NV1 == 1,1 means we don't do UNPRIV accesses */
+ if ((hcr & (HCR_NV | HCR_NV1)) != (HCR_NV | HCR_NV1)) {
+ DP_TBFLAG_A64(flags, UNPRIV, 1);
+ }
break;
case ARMMMUIdx_E20_2:
case ARMMMUIdx_E20_2_PAN:
--
2.34.1
- [PULL 08/41] target/arm: Set CTR_EL0.{IDC,DIC} for the 'max' CPU, (continued)
[PULL 11/41] target/arm: Implement HCR_EL2.AT handling, Peter Maydell, 2024/01/11
[PULL 10/41] target/arm: Handle HCR_EL2 accesses for bits introduced with FEAT_NV, Peter Maydell, 2024/01/11
[PULL 13/41] target/arm: Always honour HCR_EL2.TSC when HCR_EL2.NV is set, Peter Maydell, 2024/01/11
[PULL 16/41] target/arm: *_EL12 registers should UNDEF when HCR_EL2.E2H is 0, Peter Maydell, 2024/01/11
[PULL 28/41] target/arm: Handle HCR_EL2 accesses for FEAT_NV2 bits, Peter Maydell, 2024/01/11
[PULL 25/41] target/arm: Treat LDTR* and STTR* as LDR/STR when NV, NV1 is 1, 1,
Peter Maydell <=
[PULL 23/41] target/arm: Always use arm_pan_enabled() when checking if PAN is enabled, Peter Maydell, 2024/01/11
[PULL 15/41] target/arm: Record correct opcode fields in cpreg for E2H aliases, Peter Maydell, 2024/01/11
[PULL 34/41] target/arm: Mark up VNCR offsets (offsets 0x0..0xff), Peter Maydell, 2024/01/11
[PULL 33/41] target/arm: Report VNCR_EL2 based faults correctly, Peter Maydell, 2024/01/11
[PULL 29/41] target/arm: Implement VNCR_EL2 register, Peter Maydell, 2024/01/11
[PULL 32/41] target/arm: Implement FEAT_NV2 redirection of sysregs to RAM, Peter Maydell, 2024/01/11
[PULL 37/41] target/arm: Mark up VNCR offsets (offsets >= 0x200, except GIC), Peter Maydell, 2024/01/11
[PULL 36/41] target/arm: Mark up VNCR offsets (offsets 0x168..0x1f8), Peter Maydell, 2024/01/11
[PULL 12/41] target/arm: Enable trapping of ERET for FEAT_NV, Peter Maydell, 2024/01/11
[PULL 19/41] target/arm: Trap sysreg accesses for FEAT_NV, Peter Maydell, 2024/01/11