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[PULL 24/41] target/arm: Don't honour PSTATE.PAN when HCR_EL2.{NV, NV1}
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From: |
Peter Maydell |
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Subject: |
[PULL 24/41] target/arm: Don't honour PSTATE.PAN when HCR_EL2.{NV, NV1} == {1, 1} |
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Date: |
Thu, 11 Jan 2024 11:04:48 +0000 |
For FEAT_NV, when HCR_EL2.{NV,NV1} is {1,1} PAN is always disabled
even when the PSTATE.PAN bit is set. Implement this by having
arm_pan_enabled() return false in this situation.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Miguel Luis <miguel.luis@oracle.com>
---
target/arm/helper.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 1db2effb1c0..24751e05b24 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -266,6 +266,9 @@ void init_cpreg_list(ARMCPU *cpu)
static bool arm_pan_enabled(CPUARMState *env)
{
if (is_a64(env)) {
+ if ((arm_hcr_el2_eff(env) & (HCR_NV | HCR_NV1)) == (HCR_NV | HCR_NV1))
{
+ return false;
+ }
return env->pstate & PSTATE_PAN;
} else {
return env->uncached_cpsr & CPSR_PAN;
--
2.34.1
- [PULL 34/41] target/arm: Mark up VNCR offsets (offsets 0x0..0xff), (continued)
- [PULL 34/41] target/arm: Mark up VNCR offsets (offsets 0x0..0xff), Peter Maydell, 2024/01/11
- [PULL 33/41] target/arm: Report VNCR_EL2 based faults correctly, Peter Maydell, 2024/01/11
- [PULL 29/41] target/arm: Implement VNCR_EL2 register, Peter Maydell, 2024/01/11
- [PULL 32/41] target/arm: Implement FEAT_NV2 redirection of sysregs to RAM, Peter Maydell, 2024/01/11
- [PULL 37/41] target/arm: Mark up VNCR offsets (offsets >= 0x200, except GIC), Peter Maydell, 2024/01/11
- [PULL 36/41] target/arm: Mark up VNCR offsets (offsets 0x168..0x1f8), Peter Maydell, 2024/01/11
- [PULL 12/41] target/arm: Enable trapping of ERET for FEAT_NV, Peter Maydell, 2024/01/11
- [PULL 19/41] target/arm: Trap sysreg accesses for FEAT_NV, Peter Maydell, 2024/01/11
- [PULL 22/41] target/arm: Trap registers when HCR_EL2.{NV, NV1} == {1, 1}, Peter Maydell, 2024/01/11
- [PULL 27/41] target/arm: Add FEAT_NV to max, neoverse-n2, neoverse-v1 CPUs, Peter Maydell, 2024/01/11
- [PULL 24/41] target/arm: Don't honour PSTATE.PAN when HCR_EL2.{NV, NV1} == {1, 1},
Peter Maydell <=
- [PULL 39/41] target/arm: Report HCR_EL2.{NV,NV1,NV2} in cpu dumps, Peter Maydell, 2024/01/11
- [PULL 31/41] target/arm: Handle FEAT_NV2 redirection of SPSR_EL2, ELR_EL2, ESR_EL2, FAR_EL2, Peter Maydell, 2024/01/11
- [PULL 40/41] target/arm: Enhance CPU_LOG_INT to show SPSR on AArch64 exception-entry, Peter Maydell, 2024/01/11
- [PULL 17/41] target/arm: Make EL2 cpreg accessfns safe for FEAT_NV EL1 accesses, Peter Maydell, 2024/01/11
- [PULL 21/41] target/arm: Set SPSR_EL1.M correctly when nested virt is enabled, Peter Maydell, 2024/01/11
- [PULL 20/41] target/arm: Make NV reads of CurrentEL return EL2, Peter Maydell, 2024/01/11
- [PULL 18/41] target/arm: Move FPU/SVE/SME access checks up above ARM_CP_SPECIAL_MASK check, Peter Maydell, 2024/01/11
- [PULL 26/41] target/arm: Handle FEAT_NV page table attribute changes, Peter Maydell, 2024/01/11
- [PULL 35/41] target/arm: Mark up VNCR offsets (offsets 0x100..0x160), Peter Maydell, 2024/01/11
- [PULL 30/41] target/arm: Handle FEAT_NV2 changes to when SPSR_EL1.M reports EL2, Peter Maydell, 2024/01/11