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[PULL 39/41] target/arm: Report HCR_EL2.{NV,NV1,NV2} in cpu dumps
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From: |
Peter Maydell |
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Subject: |
[PULL 39/41] target/arm: Report HCR_EL2.{NV,NV1,NV2} in cpu dumps |
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Date: |
Thu, 11 Jan 2024 11:05:03 +0000 |
When interpreting CPU dumps where FEAT_NV and FEAT_NV2 are in use,
it's helpful to include the values of HCR_EL2.{NV,NV1,NV2} in the CPU
dump format, as a way of distinguishing when we are in EL1 as part of
executing guest-EL2 and when we are just in normal EL1.
Add the bits to the end of the log line that shows PSTATE and similar
information:
PSTATE=000003c9 ---- EL2h BTYPE=0 NV NV2
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Miguel Luis <miguel.luis@oracle.com>
---
target/arm/cpu.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index c15ad52ab3d..7d763786d88 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1059,6 +1059,7 @@ static void aarch64_cpu_dump_state(CPUState *cs, FILE *f,
int flags)
uint32_t psr = pstate_read(env);
int i, j;
int el = arm_current_el(env);
+ uint64_t hcr = arm_hcr_el2_eff(env);
const char *ns_status;
bool sve;
@@ -1096,6 +1097,10 @@ static void aarch64_cpu_dump_state(CPUState *cs, FILE
*f, int flags)
if (cpu_isar_feature(aa64_bti, cpu)) {
qemu_fprintf(f, " BTYPE=%d", (psr & PSTATE_BTYPE) >> 10);
}
+ qemu_fprintf(f, "%s%s%s",
+ (hcr & HCR_NV) ? " NV" : "",
+ (hcr & HCR_NV1) ? " NV1" : "",
+ (hcr & HCR_NV2) ? " NV2" : "");
if (!(flags & CPU_DUMP_FPU)) {
qemu_fprintf(f, "\n");
return;
--
2.34.1
- [PULL 33/41] target/arm: Report VNCR_EL2 based faults correctly, (continued)
- [PULL 33/41] target/arm: Report VNCR_EL2 based faults correctly, Peter Maydell, 2024/01/11
- [PULL 29/41] target/arm: Implement VNCR_EL2 register, Peter Maydell, 2024/01/11
- [PULL 32/41] target/arm: Implement FEAT_NV2 redirection of sysregs to RAM, Peter Maydell, 2024/01/11
- [PULL 37/41] target/arm: Mark up VNCR offsets (offsets >= 0x200, except GIC), Peter Maydell, 2024/01/11
- [PULL 36/41] target/arm: Mark up VNCR offsets (offsets 0x168..0x1f8), Peter Maydell, 2024/01/11
- [PULL 12/41] target/arm: Enable trapping of ERET for FEAT_NV, Peter Maydell, 2024/01/11
- [PULL 19/41] target/arm: Trap sysreg accesses for FEAT_NV, Peter Maydell, 2024/01/11
- [PULL 22/41] target/arm: Trap registers when HCR_EL2.{NV, NV1} == {1, 1}, Peter Maydell, 2024/01/11
- [PULL 27/41] target/arm: Add FEAT_NV to max, neoverse-n2, neoverse-v1 CPUs, Peter Maydell, 2024/01/11
- [PULL 24/41] target/arm: Don't honour PSTATE.PAN when HCR_EL2.{NV, NV1} == {1, 1}, Peter Maydell, 2024/01/11
- [PULL 39/41] target/arm: Report HCR_EL2.{NV,NV1,NV2} in cpu dumps,
Peter Maydell <=
- [PULL 31/41] target/arm: Handle FEAT_NV2 redirection of SPSR_EL2, ELR_EL2, ESR_EL2, FAR_EL2, Peter Maydell, 2024/01/11
- [PULL 40/41] target/arm: Enhance CPU_LOG_INT to show SPSR on AArch64 exception-entry, Peter Maydell, 2024/01/11
- [PULL 17/41] target/arm: Make EL2 cpreg accessfns safe for FEAT_NV EL1 accesses, Peter Maydell, 2024/01/11
- [PULL 21/41] target/arm: Set SPSR_EL1.M correctly when nested virt is enabled, Peter Maydell, 2024/01/11
- [PULL 20/41] target/arm: Make NV reads of CurrentEL return EL2, Peter Maydell, 2024/01/11
- [PULL 18/41] target/arm: Move FPU/SVE/SME access checks up above ARM_CP_SPECIAL_MASK check, Peter Maydell, 2024/01/11
- [PULL 26/41] target/arm: Handle FEAT_NV page table attribute changes, Peter Maydell, 2024/01/11
- [PULL 35/41] target/arm: Mark up VNCR offsets (offsets 0x100..0x160), Peter Maydell, 2024/01/11
- [PULL 30/41] target/arm: Handle FEAT_NV2 changes to when SPSR_EL1.M reports EL2, Peter Maydell, 2024/01/11
- Re: [PULL 00/41] target-arm queue, Peter Maydell, 2024/01/11
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