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[PULL 30/41] target/arm: Handle FEAT_NV2 changes to when SPSR_EL1.M repo
From: |
Peter Maydell |
Subject: |
[PULL 30/41] target/arm: Handle FEAT_NV2 changes to when SPSR_EL1.M reports EL2 |
Date: |
Thu, 11 Jan 2024 11:04:54 +0000 |
With FEAT_NV2, the condition for when SPSR_EL1.M should report that
an exception was taken from EL2 changes.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Miguel Luis <miguel.luis@oracle.com>
---
target/arm/helper.c | 16 ++++++++++++----
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 53bd6c85990..b9b3aaf4db7 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -11328,10 +11328,18 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
aarch64_save_sp(env, arm_current_el(env));
env->elr_el[new_el] = env->pc;
- if (cur_el == 1 && new_el == 1 &&
- ((arm_hcr_el2_eff(env) & (HCR_NV | HCR_NV1)) == HCR_NV)) {
- /* I_ZJRNN: report EL2 in the SPSR by setting M[3:2] to 0b10 */
- old_mode = deposit32(old_mode, 2, 2, 2);
+ if (cur_el == 1 && new_el == 1) {
+ uint64_t hcr = arm_hcr_el2_eff(env);
+ if ((hcr & (HCR_NV | HCR_NV1 | HCR_NV2)) == HCR_NV ||
+ (hcr & (HCR_NV | HCR_NV2)) == (HCR_NV | HCR_NV2)) {
+ /*
+ * FEAT_NV, FEAT_NV2 may need to report EL2 in the SPSR
+ * by setting M[3:2] to 0b10.
+ * If NV2 is disabled, change SPSR when NV,NV1 == 1,0 (I_ZJRNN)
+ * If NV2 is enabled, change SPSR when NV is 1 (I_DBTLM)
+ */
+ old_mode = deposit32(old_mode, 2, 2, 2);
+ }
}
} else {
old_mode = cpsr_read_for_spsr_elx(env);
--
2.34.1
- [PULL 24/41] target/arm: Don't honour PSTATE.PAN when HCR_EL2.{NV, NV1} == {1, 1}, (continued)
- [PULL 24/41] target/arm: Don't honour PSTATE.PAN when HCR_EL2.{NV, NV1} == {1, 1}, Peter Maydell, 2024/01/11
- [PULL 39/41] target/arm: Report HCR_EL2.{NV,NV1,NV2} in cpu dumps, Peter Maydell, 2024/01/11
- [PULL 31/41] target/arm: Handle FEAT_NV2 redirection of SPSR_EL2, ELR_EL2, ESR_EL2, FAR_EL2, Peter Maydell, 2024/01/11
- [PULL 40/41] target/arm: Enhance CPU_LOG_INT to show SPSR on AArch64 exception-entry, Peter Maydell, 2024/01/11
- [PULL 17/41] target/arm: Make EL2 cpreg accessfns safe for FEAT_NV EL1 accesses, Peter Maydell, 2024/01/11
- [PULL 21/41] target/arm: Set SPSR_EL1.M correctly when nested virt is enabled, Peter Maydell, 2024/01/11
- [PULL 20/41] target/arm: Make NV reads of CurrentEL return EL2, Peter Maydell, 2024/01/11
- [PULL 18/41] target/arm: Move FPU/SVE/SME access checks up above ARM_CP_SPECIAL_MASK check, Peter Maydell, 2024/01/11
- [PULL 26/41] target/arm: Handle FEAT_NV page table attribute changes, Peter Maydell, 2024/01/11
- [PULL 35/41] target/arm: Mark up VNCR offsets (offsets 0x100..0x160), Peter Maydell, 2024/01/11
- [PULL 30/41] target/arm: Handle FEAT_NV2 changes to when SPSR_EL1.M reports EL2,
Peter Maydell <=
- Re: [PULL 00/41] target-arm queue, Peter Maydell, 2024/01/11