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[PATCH rfcv1 13/23] intel_iommu: process PASID-based iotlb invalidation
From: |
Zhenzhong Duan |
Subject: |
[PATCH rfcv1 13/23] intel_iommu: process PASID-based iotlb invalidation |
Date: |
Mon, 15 Jan 2024 18:37:25 +0800 |
From: Yi Liu <yi.l.liu@intel.com>
PASID-based iotlb (piotlb) is used during walking Intel
VT-d stage-1 page table.
This adds the basic framework for piotlb invalidation,
detailed handling will be added in next patch.
Signed-off-by: Yi Liu <yi.l.liu@intel.com>
Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
---
hw/i386/intel_iommu_internal.h | 13 +++++++++
hw/i386/intel_iommu.c | 52 ++++++++++++++++++++++++++++++++++
2 files changed, 65 insertions(+)
diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h
index 65fe07c13b..40361de207 100644
--- a/hw/i386/intel_iommu_internal.h
+++ b/hw/i386/intel_iommu_internal.h
@@ -458,6 +458,19 @@ typedef union VTDInvDesc VTDInvDesc;
#define VTD_INV_DESC_PASIDC_PASID_SI (1ULL << 4)
#define VTD_INV_DESC_PASIDC_GLOBAL (3ULL << 4)
+#define VTD_INV_DESC_PIOTLB_ALL_IN_PASID (2ULL << 4)
+#define VTD_INV_DESC_PIOTLB_PSI_IN_PASID (3ULL << 4)
+
+#define VTD_INV_DESC_PIOTLB_RSVD_VAL0 0xfff000000000ffc0ULL
+#define VTD_INV_DESC_PIOTLB_RSVD_VAL1 0xf80ULL
+
+#define VTD_INV_DESC_PIOTLB_PASID(val) (((val) >> 32) & 0xfffffULL)
+#define VTD_INV_DESC_PIOTLB_DID(val) (((val) >> 16) & \
+ VTD_DOMAIN_ID_MASK)
+#define VTD_INV_DESC_PIOTLB_ADDR(val) ((val) & ~0xfffULL)
+#define VTD_INV_DESC_PIOTLB_AM(val) ((val) & 0x3fULL)
+#define VTD_INV_DESC_PIOTLB_IH(val) (((val) >> 6) & 0x1)
+
/* Information about page-selective IOTLB invalidate */
struct VTDIOTLBPageInvInfo {
uint16_t domain_id;
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index 9058be9efd..6aa44b80d6 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -3786,6 +3786,54 @@ static bool vtd_process_pasid_desc(IntelIOMMUState *s,
return !pc_info.error_happened ? true : false;
}
+static void vtd_piotlb_pasid_invalidate(IntelIOMMUState *s,
+ uint16_t domain_id, uint32_t pasid)
+{
+}
+
+static void vtd_piotlb_page_invalidate(IntelIOMMUState *s, uint16_t domain_id,
+ uint32_t pasid, hwaddr addr, uint8_t am,
+ bool ih)
+{
+}
+
+static bool vtd_process_piotlb_desc(IntelIOMMUState *s,
+ VTDInvDesc *inv_desc)
+{
+ uint16_t domain_id;
+ uint32_t pasid;
+ uint8_t am;
+ hwaddr addr;
+
+ if ((inv_desc->val[0] & VTD_INV_DESC_PIOTLB_RSVD_VAL0) ||
+ (inv_desc->val[1] & VTD_INV_DESC_PIOTLB_RSVD_VAL1)) {
+ error_report_once("non-zero-field-in-piotlb_inv_desc hi: 0x%" PRIx64
+ " lo: 0x%" PRIx64, inv_desc->val[1], inv_desc->val[0]);
+ return false;
+ }
+
+ domain_id = VTD_INV_DESC_PIOTLB_DID(inv_desc->val[0]);
+ pasid = VTD_INV_DESC_PIOTLB_PASID(inv_desc->val[0]);
+ switch (inv_desc->val[0] & VTD_INV_DESC_IOTLB_G) {
+ case VTD_INV_DESC_PIOTLB_ALL_IN_PASID:
+ vtd_piotlb_pasid_invalidate(s, domain_id, pasid);
+ break;
+
+ case VTD_INV_DESC_PIOTLB_PSI_IN_PASID:
+ am = VTD_INV_DESC_PIOTLB_AM(inv_desc->val[1]);
+ addr = (hwaddr) VTD_INV_DESC_PIOTLB_ADDR(inv_desc->val[1]);
+ vtd_piotlb_page_invalidate(s, domain_id, pasid, addr, am,
+ VTD_INV_DESC_PIOTLB_IH(inv_desc->val[1]));
+ break;
+
+ default:
+ error_report_once("Invalid granularity in P-IOTLB desc hi: 0x%" PRIx64
+ " lo: 0x%" PRIx64, inv_desc->val[1], inv_desc->val[0]);
+ return false;
+ }
+ return true;
+}
+
static bool vtd_process_inv_iec_desc(IntelIOMMUState *s,
VTDInvDesc *inv_desc)
{
@@ -3895,6 +3943,10 @@ static bool vtd_process_inv_desc(IntelIOMMUState *s)
break;
case VTD_INV_DESC_PIOTLB:
+ trace_vtd_inv_desc("p-iotlb", inv_desc.val[1], inv_desc.val[0]);
+ if (!vtd_process_piotlb_desc(s, &inv_desc)) {
+ return false;
+ }
break;
case VTD_INV_DESC_WAIT:
--
2.34.1
- [PATCH rfcv1 03/23] backends/iommufd_device: introduce IOMMUFDDevice targeted interface, (continued)
- [PATCH rfcv1 03/23] backends/iommufd_device: introduce IOMMUFDDevice targeted interface, Zhenzhong Duan, 2024/01/15
- [PATCH rfcv1 04/23] vfio: implement IOMMUFDDevice interface callbacks, Zhenzhong Duan, 2024/01/15
- [PATCH rfcv1 05/23] intel_iommu: add a placeholder variable for scalable modern mode, Zhenzhong Duan, 2024/01/15
- [PATCH rfcv1 06/23] intel_iommu: check and sync host IOMMU cap/ecap in scalable modern mode, Zhenzhong Duan, 2024/01/15
- [PATCH rfcv1 07/23] intel_iommu: process PASID cache invalidation, Zhenzhong Duan, 2024/01/15
- [PATCH rfcv1 08/23] intel_iommu: add PASID cache management infrastructure, Zhenzhong Duan, 2024/01/15
- [PATCH rfcv1 09/23] vfio/iommufd_device: Add ioas_id in IOMMUFDDevice and pass to vIOMMU, Zhenzhong Duan, 2024/01/15
- [PATCH rfcv1 10/23] intel_iommu: bind/unbind guest page table to host, Zhenzhong Duan, 2024/01/15
- [PATCH rfcv1 11/23] intel_iommu: ERRATA_772415 workaround, Zhenzhong Duan, 2024/01/15
- [PATCH rfcv1 12/23] intel_iommu: replay pasid binds after context cache invalidation, Zhenzhong Duan, 2024/01/15
- [PATCH rfcv1 13/23] intel_iommu: process PASID-based iotlb invalidation,
Zhenzhong Duan <=
- [PATCH rfcv1 14/23] intel_iommu: propagate PASID-based iotlb invalidation to host, Zhenzhong Duan, 2024/01/15
- [PATCH rfcv1 15/23] intel_iommu: process PASID-based Device-TLB invalidation, Zhenzhong Duan, 2024/01/15
- [PATCH rfcv1 16/23] intel_iommu: rename slpte in iotlb_entry to pte, Zhenzhong Duan, 2024/01/15
- [PATCH rfcv1 17/23] intel_iommu: implement firt level translation, Zhenzhong Duan, 2024/01/15
- [PATCH rfcv1 18/23] intel_iommu: fix the fault reason report, Zhenzhong Duan, 2024/01/15
- [PATCH rfcv1 21/23] intel_iommu: invalidate piotlb when flush pasid, Zhenzhong Duan, 2024/01/15
- [PATCH rfcv1 20/23] intel_iommu: piotlb invalidation should notify unmap, Zhenzhong Duan, 2024/01/15
- [PATCH rfcv1 19/23] intel_iommu: introduce pasid iotlb cache, Zhenzhong Duan, 2024/01/15
- [PATCH rfcv1 22/23] intel_iommu: refresh pasid bind after pasid cache force reset, Zhenzhong Duan, 2024/01/15
- [PATCH rfcv1 23/23] intel_iommu: modify x-scalable-mode to be string option, Zhenzhong Duan, 2024/01/15