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[PATCH v8 01/21] hw/core/machine: Introduce the module as a CPU topology
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From: |
Zhao Liu |
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Subject: |
[PATCH v8 01/21] hw/core/machine: Introduce the module as a CPU topology level |
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Date: |
Wed, 31 Jan 2024 18:13:30 +0800 |
From: Zhao Liu <zhao1.liu@intel.com>
In x86, module is the topology level above core, which contains a set
of cores that share certain resources (in current products, the resource
usually includes L2 cache, as well as module scoped features and MSRs).
To build the module level topology for x86 CPUs, introduce module level
support in MachineState and MachineClass.
Suggested-by: Xiaoyao Li <xiaoyao.li@intel.com>
Tested-by: Yongwei Ma <yongwei.ma@intel.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
---
Changes since v7:
* New commit to introduce module level in -smp.
---
hw/core/machine-smp.c | 2 +-
hw/core/machine.c | 1 +
include/hw/boards.h | 4 ++++
3 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/hw/core/machine-smp.c b/hw/core/machine-smp.c
index 25019c91ee36..a0a30da59aa4 100644
--- a/hw/core/machine-smp.c
+++ b/hw/core/machine-smp.c
@@ -234,7 +234,7 @@ void machine_parse_smp_config(MachineState *ms,
unsigned int machine_topo_get_cores_per_socket(const MachineState *ms)
{
- return ms->smp.cores * ms->smp.clusters * ms->smp.dies;
+ return ms->smp.cores * ms->smp.modules * ms->smp.clusters * ms->smp.dies;
}
unsigned int machine_topo_get_threads_per_socket(const MachineState *ms)
diff --git a/hw/core/machine.c b/hw/core/machine.c
index fb5afdcae4cc..36fe3a4806f2 100644
--- a/hw/core/machine.c
+++ b/hw/core/machine.c
@@ -1148,6 +1148,7 @@ static void machine_initfn(Object *obj)
ms->smp.sockets = 1;
ms->smp.dies = 1;
ms->smp.clusters = 1;
+ ms->smp.modules = 1;
ms->smp.cores = 1;
ms->smp.threads = 1;
diff --git a/include/hw/boards.h b/include/hw/boards.h
index bcfde8a84d10..78dea50054a1 100644
--- a/include/hw/boards.h
+++ b/include/hw/boards.h
@@ -143,6 +143,7 @@ typedef struct {
* provided SMP configuration
* @books_supported - whether books are supported by the machine
* @drawers_supported - whether drawers are supported by the machine
+ * @modules_supported - whether modules are supported by the machine
*/
typedef struct {
bool prefer_sockets;
@@ -151,6 +152,7 @@ typedef struct {
bool has_clusters;
bool books_supported;
bool drawers_supported;
+ bool modules_supported;
} SMPCompatProps;
/**
@@ -338,6 +340,7 @@ typedef struct DeviceMemoryState {
* @sockets: the number of sockets in one book
* @dies: the number of dies in one socket
* @clusters: the number of clusters in one die
+ * @modules: the number of modules in one cluster
* @cores: the number of cores in one cluster
* @threads: the number of threads in one core
* @max_cpus: the maximum number of logical processors on the machine
@@ -349,6 +352,7 @@ typedef struct CpuTopology {
unsigned int sockets;
unsigned int dies;
unsigned int clusters;
+ unsigned int modules;
unsigned int cores;
unsigned int threads;
unsigned int max_cpus;
--
2.34.1
- [PATCH v8 00/21] Introduce smp.modules for x86 in QEMU, Zhao Liu, 2024/01/31
- [PATCH v8 01/21] hw/core/machine: Introduce the module as a CPU topology level,
Zhao Liu <=
- [PATCH v8 02/21] hw/core/machine: Support modules in -smp, Zhao Liu, 2024/01/31
- [PATCH v8 05/21] i386/cpu: Fix i/d-cache topology to core level for Intel CPU, Zhao Liu, 2024/01/31
- [PATCH v8 03/21] hw/core: Introduce module-id as the topology subindex, Zhao Liu, 2024/01/31
- [PATCH v8 04/21] hw/core: Support module-id in numa configuration, Zhao Liu, 2024/01/31
- [PATCH v8 07/21] i386/cpu: Use APIC ID info get NumSharingCache for CPUID[0x8000001D].EAX[bits 25:14], Zhao Liu, 2024/01/31
- [PATCH v8 06/21] i386/cpu: Use APIC ID info to encode cache topo in CPUID[4], Zhao Liu, 2024/01/31
- [PATCH v8 08/21] i386/cpu: Consolidate the use of topo_info in cpu_x86_cpuid(), Zhao Liu, 2024/01/31
- [PATCH v8 10/21] i386: Split topology types of CPUID[0x1F] from the definitions of CPUID[0xB], Zhao Liu, 2024/01/31
- [PATCH v8 09/21] i386/cpu: Introduce bitmap to cache available CPU topology levels, Zhao Liu, 2024/01/31
- [PATCH v8 11/21] i386/cpu: Decouple CPUID[0x1F] subleaf with specific topology level, Zhao Liu, 2024/01/31