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[PATCH v10 04/21] hw/core: Support module-id in numa configuration
From: |
Zhao Liu |
Subject: |
[PATCH v10 04/21] hw/core: Support module-id in numa configuration |
Date: |
Thu, 21 Mar 2024 22:40:31 +0800 |
From: Zhao Liu <zhao1.liu@intel.com>
Module is a level above the core, thereby supporting numa
configuration on the module level can bring user more numa flexibility.
This is the natural further support for module level.
Add module level support in numa configuration.
Tested-by: Yongwei Ma <yongwei.ma@intel.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Tested-by: Babu Moger <babu.moger@amd.com>
---
Changes since v7:
* New commit to support module level.
---
hw/core/machine.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/hw/core/machine.c b/hw/core/machine.c
index 9ff5170f8e31..27340392aec8 100644
--- a/hw/core/machine.c
+++ b/hw/core/machine.c
@@ -797,6 +797,11 @@ void machine_set_cpu_numa_node(MachineState *machine,
return;
}
+ if (props->has_module_id && !slot->props.has_module_id) {
+ error_setg(errp, "module-id is not supported");
+ return;
+ }
+
if (props->has_cluster_id && !slot->props.has_cluster_id) {
error_setg(errp, "cluster-id is not supported");
return;
@@ -821,6 +826,11 @@ void machine_set_cpu_numa_node(MachineState *machine,
continue;
}
+ if (props->has_module_id &&
+ props->module_id != slot->props.module_id) {
+ continue;
+ }
+
if (props->has_cluster_id &&
props->cluster_id != slot->props.cluster_id) {
continue;
@@ -1218,6 +1228,12 @@ static char *cpu_slot_to_string(const CPUArchId *cpu)
}
g_string_append_printf(s, "cluster-id: %"PRId64,
cpu->props.cluster_id);
}
+ if (cpu->props.has_module_id) {
+ if (s->len) {
+ g_string_append_printf(s, ", ");
+ }
+ g_string_append_printf(s, "module-id: %"PRId64, cpu->props.module_id);
+ }
if (cpu->props.has_core_id) {
if (s->len) {
g_string_append_printf(s, ", ");
--
2.34.1
- [PATCH v10 00/21] i386: Introduce smp.modules and clean up cache topology, Zhao Liu, 2024/03/21
- [PATCH v10 01/21] hw/core/machine: Introduce the module as a CPU topology level, Zhao Liu, 2024/03/21
- [PATCH v10 02/21] hw/core/machine: Support modules in -smp, Zhao Liu, 2024/03/21
- [PATCH v10 03/21] hw/core: Introduce module-id as the topology subindex, Zhao Liu, 2024/03/21
- [PATCH v10 04/21] hw/core: Support module-id in numa configuration,
Zhao Liu <=
- [PATCH v10 05/21] i386/cpu: Fix i/d-cache topology to core level for Intel CPU, Zhao Liu, 2024/03/21
- [PATCH v10 06/21] i386/cpu: Use APIC ID info to encode cache topo in CPUID[4], Zhao Liu, 2024/03/21
- [PATCH v10 07/21] i386/cpu: Use APIC ID info get NumSharingCache for CPUID[0x8000001D].EAX[bits 25:14], Zhao Liu, 2024/03/21
- [PATCH v10 08/21] i386/cpu: Consolidate the use of topo_info in cpu_x86_cpuid(), Zhao Liu, 2024/03/21
- [PATCH v10 09/21] i386/cpu: Introduce bitmap to cache available CPU topology levels, Zhao Liu, 2024/03/21
- [PATCH v10 10/21] i386: Split topology types of CPUID[0x1F] from the definitions of CPUID[0xB], Zhao Liu, 2024/03/21
- [PATCH v10 12/21] i386: Introduce module level cpu topology to CPUX86State, Zhao Liu, 2024/03/21
- [PATCH v10 11/21] i386/cpu: Decouple CPUID[0x1F] subleaf with specific topology level, Zhao Liu, 2024/03/21
- [PATCH v10 13/21] i386: Support modules_per_die in X86CPUTopoInfo, Zhao Liu, 2024/03/21
- [PATCH v10 14/21] i386: Expose module level in CPUID[0x1F], Zhao Liu, 2024/03/21