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[PULL 28/38] target/sparc: Enable VIS3 feature bit
From: |
Richard Henderson |
Subject: |
[PULL 28/38] target/sparc: Enable VIS3 feature bit |
Date: |
Wed, 5 Jun 2024 10:22:43 -0700 |
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
linux-user/elfload.c | 1 +
target/sparc/cpu.c | 3 +++
2 files changed, 4 insertions(+)
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
index 6a1457346a..cb79580431 100644
--- a/linux-user/elfload.c
+++ b/linux-user/elfload.c
@@ -1004,6 +1004,7 @@ static uint32_t get_elf_hwcap(void)
r |= features & CPU_FEATURE_VIS1 ? HWCAP_SPARC_VIS : 0;
r |= features & CPU_FEATURE_VIS2 ? HWCAP_SPARC_VIS2 : 0;
r |= features & CPU_FEATURE_FMAF ? HWCAP_SPARC_FMAF : 0;
+ r |= features & CPU_FEATURE_VIS3 ? HWCAP_SPARC_VIS3 : 0;
#endif
return r;
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index ed9238a69d..8ea977b49f 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -550,6 +550,7 @@ static const char * const feature_name[] = {
[CPU_FEATURE_BIT_VIS1] = "vis1",
[CPU_FEATURE_BIT_VIS2] = "vis2",
[CPU_FEATURE_BIT_FMAF] = "fmaf",
+ [CPU_FEATURE_BIT_VIS3] = "vis3",
#else
[CPU_FEATURE_BIT_MUL] = "mul",
[CPU_FEATURE_BIT_DIV] = "div",
@@ -880,6 +881,8 @@ static Property sparc_cpu_properties[] = {
CPU_FEATURE_BIT_VIS2, false),
DEFINE_PROP_BIT("fmaf", SPARCCPU, env.def.features,
CPU_FEATURE_BIT_FMAF, false),
+ DEFINE_PROP_BIT("vis3", SPARCCPU, env.def.features,
+ CPU_FEATURE_BIT_VIS3, false),
#else
DEFINE_PROP_BIT("mul", SPARCCPU, env.def.features,
CPU_FEATURE_BIT_MUL, false),
--
2.34.1
- [PULL 19/38] target/sparc: Implement FPADDS, FPSUBS, (continued)
- [PULL 19/38] target/sparc: Implement FPADDS, FPSUBS, Richard Henderson, 2024/06/05
- [PULL 20/38] target/sparc: Implement FPCMPEQ8, FPCMPNE8, FPCMPULE8, FPCMPUGT8, Richard Henderson, 2024/06/05
- [PULL 21/38] target/sparc: Implement FSLL, FSRL, FSRA, FSLAS, Richard Henderson, 2024/06/05
- [PULL 15/38] target/sparc: Implement FHADD, FHSUB, FNHADD, FNADD, FNMUL, Richard Henderson, 2024/06/05
- [PULL 22/38] target/sparc: Implement LDXEFSR, Richard Henderson, 2024/06/05
- [PULL 23/38] target/sparc: Implement LZCNT, Richard Henderson, 2024/06/05
- [PULL 24/38] target/sparc: Implement MOVsTOw, MOVdTOx, MOVwTOs, MOVxTOd, Richard Henderson, 2024/06/05
- [PULL 25/38] target/sparc: Implement PDISTN, Richard Henderson, 2024/06/05
- [PULL 26/38] target/sparc: Implement UMULXHI, Richard Henderson, 2024/06/05
- [PULL 27/38] target/sparc: Implement XMULX, Richard Henderson, 2024/06/05
- [PULL 28/38] target/sparc: Enable VIS3 feature bit,
Richard Henderson <=
- [PULL 29/38] target/sparc: Implement IMA extension, Richard Henderson, 2024/06/05
- [PULL 30/38] target/sparc: Add feature bit for VIS4, Richard Henderson, 2024/06/05
- [PULL 31/38] target/sparc: Implement FALIGNDATAi, Richard Henderson, 2024/06/05
- [PULL 32/38] target/sparc: Implement 8-bit FPADD, FPADDS, and FPADDUS, Richard Henderson, 2024/06/05
- [PULL 33/38] target/sparc: Implement VIS4 comparisons, Richard Henderson, 2024/06/05
- [PULL 34/38] target/sparc: Implement FPMIN, FPMAX, Richard Henderson, 2024/06/05
- [PULL 35/38] target/sparc: Implement SUBXC, SUBXCcc, Richard Henderson, 2024/06/05
- [PULL 36/38] target/sparc: Implement MWAIT, Richard Henderson, 2024/06/05
- [PULL 37/38] target/sparc: Implement monitor ASIs, Richard Henderson, 2024/06/05
- [PULL 38/38] target/sparc: Enable VIS4 feature bit, Richard Henderson, 2024/06/05