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[Stable-8.2.5 38/45] target/riscv: do not set mtval2 for non guest-page
From: |
Michael Tokarev |
Subject: |
[Stable-8.2.5 38/45] target/riscv: do not set mtval2 for non guest-page faults |
Date: |
Fri, 7 Jun 2024 22:12:57 +0300 |
From: Alexei Filippov <alexei.filippov@syntacore.com>
Previous patch fixed the PMP priority in raise_mmu_exception() but we're still
setting mtval2 incorrectly. In riscv_cpu_tlb_fill(), after pmp check in 2 stage
translation part, mtval2 will be set in case of successes 2 stage translation
but
failed pmp check.
In this case we gonna set mtval2 via env->guest_phys_fault_addr in context of
riscv_cpu_tlb_fill(), as this was a guest-page-fault, but it didn't and mtval2
should be zero, according to RISCV privileged spec sect. 9.4.4: When a guest
page-fault is taken into M-mode, mtval2 is written with either zero or guest
physical address that faulted, shifted by 2 bits. *For other traps, mtval2
is set to zero...*
Signed-off-by: Alexei Filippov <alexei.filippov@syntacore.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240503103052.6819-1-alexei.filippov@syntacore.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
(cherry picked from commit 6c9a344247132ac6c3d0eb9670db45149a29c88f)
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index cf97c782dd..62dda4f284 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -1361,17 +1361,17 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address,
int size,
__func__, pa, ret, prot_pmp, tlb_size);
prot &= prot_pmp;
- }
-
- if (ret != TRANSLATE_SUCCESS) {
+ } else {
/*
* Guest physical address translation failed, this is a HS
* level exception
*/
first_stage_error = false;
- env->guest_phys_fault_addr = (im_address |
- (address &
- (TARGET_PAGE_SIZE - 1))) >> 2;
+ if (ret != TRANSLATE_PMP_FAIL) {
+ env->guest_phys_fault_addr = (im_address |
+ (address &
+ (TARGET_PAGE_SIZE - 1))) >>
2;
+ }
}
}
} else {
--
2.39.2
- [Stable-8.2.5 30/45] target/riscv/kvm: tolerate KVM disable ext errors, (continued)
- [Stable-8.2.5 30/45] target/riscv/kvm: tolerate KVM disable ext errors, Michael Tokarev, 2024/06/07
- [Stable-8.2.5 27/45] qio: Inherit follow_coroutine_ctx across TLS, Michael Tokarev, 2024/06/07
- [Stable-8.2.5 28/45] iotests: test NBD+TLS+iothread, Michael Tokarev, 2024/06/07
- [Stable-8.2.5 31/45] target/riscv: Fix the element agnostic function problem, Michael Tokarev, 2024/06/07
- [Stable-8.2.5 32/45] target/riscv/cpu.c: fix Zvkb extension config, Michael Tokarev, 2024/06/07
- [Stable-8.2.5 33/45] target/riscv: rvv: Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions, Michael Tokarev, 2024/06/07
- [Stable-8.2.5 34/45] target/riscv: rvv: Check single width operator for vector fp widen instructions, Michael Tokarev, 2024/06/07
- [Stable-8.2.5 35/45] target/riscv: rvv: Check single width operator for vfncvt.rod.f.f.w, Michael Tokarev, 2024/06/07
- [Stable-8.2.5 36/45] target/riscv: rvv: Remove redudant SEW checking for vector fp narrow/widen instructions, Michael Tokarev, 2024/06/07
- [Stable-8.2.5 37/45] target/riscv: prioritize pmp errors in raise_mmu_exception(), Michael Tokarev, 2024/06/07
- [Stable-8.2.5 38/45] target/riscv: do not set mtval2 for non guest-page faults,
Michael Tokarev <=
- [Stable-8.2.5 39/45] target/riscv: rvzicbo: Fixup CBO extension register calculation, Michael Tokarev, 2024/06/07
- [Stable-8.2.5 40/45] target/riscv/kvm.c: Fix the hart bit setting of AIA, Michael Tokarev, 2024/06/07
- [Stable-8.2.5 41/45] disas/riscv: Decode all of the pmpcfg and pmpaddr CSRs, Michael Tokarev, 2024/06/07
- [Stable-8.2.5 42/45] target/i386: fix xsave.flat from kvm-unit-tests, Michael Tokarev, 2024/06/07
- [Stable-8.2.5 43/45] target/i386: fix SSE and SSE2 feature check, Michael Tokarev, 2024/06/07
- [Stable-8.2.5 44/45] ui/sdl2: Allow host to power down screen, Michael Tokarev, 2024/06/07
- [Stable-8.2.5 45/45] target/loongarch: fix a wrong print in cpu dump, Michael Tokarev, 2024/06/07