Re: [PATCH v2] Hexagon: lldb read/write predicate registers p0/p1/p2/p3

[Matheus Tavares Bernardino]

On Thu, 13 Jun 2024 12:22:09 -0600 Taylor Simpson <ltaylorsimpson@gmail.com> 
wrote:
>
> hexagon-core.xml only exposes register p3_0 which is an alias that
> aggregates the predicate registers.  It is more convenient for users
> to interact directly with the predicate registers.
> 
> Tested with lldb downloaded from this location
> https://github.com/llvm/llvm-project/releases/download/llvmorg-18.1.4/clang+llvm-18.1.4-x86_64-linux-gnu-ubuntu-18.04.tar.xz
> 
> BEFORE:
> (lldb) reg read p3_0
>     p3_0 = 0x00000000
> (lldb) reg read p0
> error: Invalid register name 'p0'.
> (lldb) reg write p1 0xf
> error: Register not found for 'p1'.
> 
> AFTER:
> (lldb) reg read p3_0
>     p3_0 = 0x00000000
> (lldb) reg read p0
>       p0 = 0x00
> (lldb) reg read -s 1
> Predicate Registers:
>         p0 = 0x00
>         p1 = 0x00
>         p2 = 0x00
>         p3 = 0x00
> 
> (lldb) reg write p1 0xf
> (lldb) reg read p3_0
>     p3_0 = 0x00000f00
> (lldb) reg write p3_0 0xff00ff00
> (lldb) reg read -s 1
> Predicate Registers:
>         p0 = 0x00
>         p1 = 0xff
>         p2 = 0x00
>         p3 = 0xff
> 
> Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com>

Reviewed-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com>