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[PULL 02/24] tcg/loongarch64: Use fp load/store for I32 and I64 into vec
From: |
Richard Henderson |
Subject: |
[PULL 02/24] tcg/loongarch64: Use fp load/store for I32 and I64 into vector regs |
Date: |
Wed, 19 Jun 2024 13:59:30 -0700 |
Reviewed-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/loongarch64/tcg-target.c.inc | 36 +++++++++-----------------------
1 file changed, 10 insertions(+), 26 deletions(-)
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
index 06ca1ab11c..b9078ac793 100644
--- a/tcg/loongarch64/tcg-target.c.inc
+++ b/tcg/loongarch64/tcg-target.c.inc
@@ -803,6 +803,12 @@ static void tcg_out_ldst(TCGContext *s, LoongArchInsn opc,
TCGReg data,
case OPC_ST_D:
tcg_out32(s, encode_djsk12_insn(opc, data, addr, imm12));
break;
+ case OPC_FLD_S:
+ case OPC_FLD_D:
+ case OPC_FST_S:
+ case OPC_FST_D:
+ tcg_out32(s, encode_fdjsk12_insn(opc, data, addr, imm12));
+ break;
default:
g_assert_not_reached();
}
@@ -816,14 +822,14 @@ static void tcg_out_ld(TCGContext *s, TCGType type,
TCGReg dest,
if (dest < TCG_REG_V0) {
tcg_out_ldst(s, OPC_LD_W, dest, base, offset);
} else {
- tcg_out_dupm_vec(s, TCG_TYPE_I128, MO_32, dest, base, offset);
+ tcg_out_ldst(s, OPC_FLD_S, dest, base, offset);
}
break;
case TCG_TYPE_I64:
if (dest < TCG_REG_V0) {
tcg_out_ldst(s, OPC_LD_D, dest, base, offset);
} else {
- tcg_out_dupm_vec(s, TCG_TYPE_I128, MO_64, dest, base, offset);
+ tcg_out_ldst(s, OPC_FLD_D, dest, base, offset);
}
break;
case TCG_TYPE_V128:
@@ -847,36 +853,14 @@ static void tcg_out_st(TCGContext *s, TCGType type,
TCGReg src,
if (src < TCG_REG_V0) {
tcg_out_ldst(s, OPC_ST_W, src, base, offset);
} else {
- /* TODO: Could use fst_s, fstx_s */
- if (offset < -0x100 || offset > 0xff || (offset & 3)) {
- if (-0x800 <= offset && offset <= 0x7ff) {
- tcg_out_opc_addi_d(s, TCG_REG_TMP0, base, offset);
- } else {
- tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP0, offset);
- tcg_out_opc_add_d(s, TCG_REG_TMP0, TCG_REG_TMP0, base);
- }
- base = TCG_REG_TMP0;
- offset = 0;
- }
- tcg_out_opc_vstelm_w(s, src, base, offset, 0);
+ tcg_out_ldst(s, OPC_FST_S, src, base, offset);
}
break;
case TCG_TYPE_I64:
if (src < TCG_REG_V0) {
tcg_out_ldst(s, OPC_ST_D, src, base, offset);
} else {
- /* TODO: Could use fst_d, fstx_d */
- if (offset < -0x100 || offset > 0xff || (offset & 7)) {
- if (-0x800 <= offset && offset <= 0x7ff) {
- tcg_out_opc_addi_d(s, TCG_REG_TMP0, base, offset);
- } else {
- tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP0, offset);
- tcg_out_opc_add_d(s, TCG_REG_TMP0, TCG_REG_TMP0, base);
- }
- base = TCG_REG_TMP0;
- offset = 0;
- }
- tcg_out_opc_vstelm_d(s, src, base, offset, 0);
+ tcg_out_ldst(s, OPC_FST_D, src, base, offset);
}
break;
case TCG_TYPE_V128:
--
2.34.1
- [PULL 00/24] tcg patch queue, Richard Henderson, 2024/06/19
- [PULL 04/24] tcg/loongarch64: Support TCG_TYPE_V64, Richard Henderson, 2024/06/19
- [PULL 05/24] util/loongarch64: Detect LASX vector support, Richard Henderson, 2024/06/19
- [PULL 02/24] tcg/loongarch64: Use fp load/store for I32 and I64 into vector regs,
Richard Henderson <=
- [PULL 03/24] tcg/loongarch64: Handle i32 and i64 moves between gr and fr, Richard Henderson, 2024/06/19
- [PULL 01/24] tcg/loongarch64: Import LASX, FP insns, Richard Henderson, 2024/06/19
- [PULL 10/24] tcg/loongarch64: Support LASX in tcg_out_dupi_vec, Richard Henderson, 2024/06/19
- [PULL 08/24] tcg/loongarch64: Support LASX in tcg_out_dupm_vec, Richard Henderson, 2024/06/19
- [PULL 09/24] tcg/loongarch64: Use tcg_out_dup_vec in tcg_out_dupi_vec, Richard Henderson, 2024/06/19
- [PULL 12/24] tcg/loongarch64: Support LASX in tcg_out_addsub_vec, Richard Henderson, 2024/06/19
- [PULL 06/24] tcg/loongarch64: Simplify tcg_out_dup_vec, Richard Henderson, 2024/06/19
- [PULL 07/24] tcg/loongarch64: Support LASX in tcg_out_dup_vec, Richard Henderson, 2024/06/19
- [PULL 11/24] tcg/loongarch64: Simplify tcg_out_addsub_vec, Richard Henderson, 2024/06/19
- [PULL 13/24] tcg/loongarch64: Split out vdvjvk in tcg_out_vec_op, Richard Henderson, 2024/06/19