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[PULL 10/32] hw/riscv/virt.c: imsics DT: add 'qemu, imsics' to 'compatib
From: |
Alistair Francis |
Subject: |
[PULL 10/32] hw/riscv/virt.c: imsics DT: add 'qemu, imsics' to 'compatible' |
Date: |
Thu, 27 Jun 2024 20:00:31 +1000 |
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
The DT docs for riscv,imsics [1] predicts a 'qemu,imsics' enum in the
'compatible' property.
[1] Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.yaml
Reported-by: Conor Dooley <conor@kernel.org>
Fixes: 28d8c281200f ("hw/riscv: virt: Add optional AIA IMSIC support to virt
machine")
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240531202759.911601-8-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/virt.c | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 376e362a68..e1ecf79551 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -515,6 +515,9 @@ static void create_fdt_one_imsic(RISCVVirtState *s, hwaddr
base_addr,
uint32_t imsic_max_hart_per_socket, imsic_addr, imsic_size;
g_autofree uint32_t *imsic_cells = NULL;
g_autofree uint32_t *imsic_regs = NULL;
+ static const char * const imsic_compat[2] = {
+ "qemu,imsics", "riscv,imsics"
+ };
imsic_cells = g_new0(uint32_t, ms->smp.cpus * 2);
imsic_regs = g_new0(uint32_t, socket_count * 4);
@@ -541,7 +544,10 @@ static void create_fdt_one_imsic(RISCVVirtState *s, hwaddr
base_addr,
imsic_name = g_strdup_printf("/soc/interrupt-controller@%lx",
(unsigned long)base_addr);
qemu_fdt_add_subnode(ms->fdt, imsic_name);
- qemu_fdt_setprop_string(ms->fdt, imsic_name, "compatible", "riscv,imsics");
+ qemu_fdt_setprop_string_array(ms->fdt, imsic_name, "compatible",
+ (char **)&imsic_compat,
+ ARRAY_SIZE(imsic_compat));
+
qemu_fdt_setprop_cell(ms->fdt, imsic_name, "#interrupt-cells",
FDT_IMSIC_INT_CELLS);
qemu_fdt_setprop(ms->fdt, imsic_name, "interrupt-controller", NULL, 0);
--
2.45.2
- [PULL 00/32] riscv-to-apply queue, Alistair Francis, 2024/06/27
- [PULL 01/32] target/riscv: Extend virtual irq csrs masks to be 64 bit wide., Alistair Francis, 2024/06/27
- [PULL 02/32] target/riscv: Move Guest irqs out of the core local irqs range., Alistair Francis, 2024/06/27
- [PULL 03/32] target/riscv: zvbb implies zvkb, Alistair Francis, 2024/06/27
- [PULL 05/32] hw/riscv/virt.c: add aplic nodename helper, Alistair Francis, 2024/06/27
- [PULL 04/32] hw/riscv/virt.c: add address-cells in create_fdt_one_aplic(), Alistair Francis, 2024/06/27
- [PULL 07/32] hw/riscv/virt.c: aplic DT: add 'qemu, aplic' to 'compatible', Alistair Francis, 2024/06/27
- [PULL 08/32] hw/riscv/virt.c: aplic DT: rename prop to 'riscv, delegation', Alistair Francis, 2024/06/27
- [PULL 06/32] hw/riscv/virt.c: rename aplic nodename to 'interrupt-controller', Alistair Francis, 2024/06/27
- [PULL 09/32] hw/riscv/virt.c: change imsic nodename to 'interrupt-controller', Alistair Francis, 2024/06/27
- [PULL 10/32] hw/riscv/virt.c: imsics DT: add 'qemu, imsics' to 'compatible',
Alistair Francis <=
- [PULL 11/32] hw/riscv/virt.c: imsics DT: add '#msi-cells', Alistair Francis, 2024/06/27
- [PULL 13/32] target/riscv/kvm: handle the exit with debug reason, Alistair Francis, 2024/06/27
- [PULL 14/32] target/riscv/kvm: define TARGET_KVM_HAVE_GUEST_DEBUG, Alistair Francis, 2024/06/27
- [PULL 12/32] target/riscv/kvm: add software breakpoints support, Alistair Francis, 2024/06/27
- [PULL 16/32] target/riscv: Define macros and variables for ss1p13, Alistair Francis, 2024/06/27
- [PULL 17/32] target/riscv: Add 'P1P13' bit in SMSTATEEN0, Alistair Francis, 2024/06/27
- [PULL 15/32] target/riscv: Reuse the conversion function of priv_spec, Alistair Francis, 2024/06/27
- [PULL 18/32] target/riscv: Add MEDELEGH, HEDELEGH csrs for RV32, Alistair Francis, 2024/06/27
- [PULL 19/32] target/riscv: Reserve exception codes for sw-check and hw-err, Alistair Francis, 2024/06/27
- [PULL 20/32] target/riscv: Support the version for ss1p13, Alistair Francis, 2024/06/27