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[PATCH 1/9] target/arm: Correct comments about M-profile FPSCR
From: |
Peter Maydell |
Subject: |
[PATCH 1/9] target/arm: Correct comments about M-profile FPSCR |
Date: |
Fri, 28 Jun 2024 15:23:39 +0100 |
The M-profile FPSCR LTPSIZE is bits [18:16]; this is the same
field as A-profile FPSCR Len, not Stride. Correct the comment
in vfp_get_fpscr().
We also implemented M-profile FPSCR.QC, but forgot to delete
a TODO comment from vfp_set_fpscr(); remove it now.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/vfp_helper.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
index ce26b8a71a1..dd67825270b 100644
--- a/target/arm/vfp_helper.c
+++ b/target/arm/vfp_helper.c
@@ -176,8 +176,8 @@ uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
| (env->vfp.vec_stride << 20);
/*
- * M-profile LTPSIZE overlaps A-profile Stride; whichever of the
- * two is not applicable to this CPU will always be zero.
+ * M-profile LTPSIZE is the same bits [18:16] as A-profile Len; whichever
+ * of the two is not applicable to this CPU will always be zero.
*/
fpscr |= env->v7m.ltpsize << 16;
@@ -226,7 +226,6 @@ void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
/*
* The bit we set within fpscr_q is arbitrary; the register as a
* whole being zero/non-zero is what counts.
- * TODO: M-profile MVE also has a QC bit.
*/
env->vfp.qc[0] = val & FPCR_QC;
env->vfp.qc[1] = 0;
--
2.34.1
- [PATCH 0/9] target/arm: Refactor FPCR/FPSR handling to prepare for FEAT_AFP, Peter Maydell, 2024/06/28
- [PATCH 1/9] target/arm: Correct comments about M-profile FPSCR,
Peter Maydell <=
- [PATCH 2/9] target/arm: Make vfp_get_fpscr() call vfp_get_{fpcr, fpsr}, Peter Maydell, 2024/06/28
- [PATCH 5/9] target/arm: Implement store_cpu_field_low32() macro, Peter Maydell, 2024/06/28
- [PATCH 9/9] target/arm: Allow FPCR bits that aren't in FPSCR, Peter Maydell, 2024/06/28
- [PATCH 6/9] target/arm: Store FPSR and FPCR in separate CPU state fields, Peter Maydell, 2024/06/28
- [PATCH 8/9] target/arm: Rename FPSR_MASK and FPCR_MASK and define them symbolically, Peter Maydell, 2024/06/28