Re: [PATCH 02/23] target/i386: fix gen_prepare_size_nz condition

[Igor Mammedov]

On Fri, 28 Jun 2024 15:34:58 +0100
Alex Bennée <alex.bennee@linaro.org> wrote:

> Alex Bennée <alex.bennee@linaro.org> writes:
> 
> > Incorrect brace positions causes an unintended overflow on 32 bit
> > builds and shenanigans result.
> >
> > Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2413
> > Suggested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
> > Signed-off-by: Alex Bennée <alex.bennee@linaro.org>  
> 
> This seems to trigger regressions in:
> 
>   qtest-x86_64/bios-tables-test
>   qtest-x86_64/pxe-test
>   qtest-x86_64/vmgenid-test
> 
> Could that be down to generated test data?

Without context, I'd guess, that
guest doesn't boot/get to randevu point that tests are waiting for
and then it just timeouts => fails.

> 
> > ---
> >  target/i386/tcg/translate.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
> > index ad1819815a..94f13541c3 100644
> > --- a/target/i386/tcg/translate.c
> > +++ b/target/i386/tcg/translate.c
> > @@ -877,7 +877,7 @@ static CCPrepare gen_prepare_sign_nz(TCGv src, MemOp 
> > size)
> >          return (CCPrepare) { .cond = TCG_COND_LT, .reg = src };
> >      } else {
> >          return (CCPrepare) { .cond = TCG_COND_TSTNE, .reg = src,
> > -                             .imm = 1ull << ((8 << size) - 1) };
> > +                             .imm = (1ull << (8 << size)) - 1 };
> >      }
> >  }  
>