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[PULL 0/7] tcg patch queue


From: Richard Henderson
Subject: [PULL 0/7] tcg patch queue
Date: Wed, 3 Jul 2024 10:42:19 -0700

The following changes since commit 6746482d12da3b6e4d3cdf06481a0027a797f719:

  Merge tag 'sdmmc-20240702' of https://github.com/philmd/qemu into staging 
(2024-07-02 09:52:10 -0700)

are available in the Git repository at:

  https://gitlab.com/rth7680/qemu tags/pull-tcg-20240703

for you to fetch changes up to a71d9dfbf63db42d6e6ae87fc112d1f5502183bd:

  tcg/optimize: Fix TCG_COND_TST* simplification of setcond2 (2024-07-03 
10:24:12 -0700)

----------------------------------------------------------------
util: cpuinfo portability fixes for FreeBSD and OpenBSD
util: cpuinfo for riscv host
tcg/optimize: Fix TCG_COND_TST* simplification of setcond2

----------------------------------------------------------------
Brad Smith (3):
      util/cpuinfo-ppc: Fix building on OpenBSD
      util/cpuinfo-ppc: Add FreeBSD support
      util/cpuinfo-aarch64: Add OpenBSD support

Richard Henderson (4):
      util/cpuinfo-riscv: Support host/cpuinfo.h for riscv
      util/cpuinfo-riscv: Support OpenBSD signal frame
      util/cpuinfo-riscv: Use linux __riscv_hwprobe syscall
      tcg/optimize: Fix TCG_COND_TST* simplification of setcond2

 meson.build                       |   6 ++
 host/include/riscv/host/cpuinfo.h |  23 ++++++++
 tcg/riscv/tcg-target.h            |  46 +++++++--------
 tcg/optimize.c                    |   2 +-
 tests/tcg/x86_64/test-2413.c      |  30 ++++++++++
 util/cpuinfo-aarch64.c            |  36 ++++++++++++
 util/cpuinfo-ppc.c                |  27 ++++++---
 util/cpuinfo-riscv.c              | 118 ++++++++++++++++++++++++++++++++++++++
 tcg/riscv/tcg-target.c.inc        |  84 +++------------------------
 tests/tcg/x86_64/Makefile.target  |   2 +
 util/meson.build                  |   2 +
 11 files changed, 266 insertions(+), 110 deletions(-)
 create mode 100644 host/include/riscv/host/cpuinfo.h
 create mode 100644 tests/tcg/x86_64/test-2413.c
 create mode 100644 util/cpuinfo-riscv.c



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