Re: [PATCH] target/riscv: Fix the check with vector register multiples of LMUL

[Alistair Francis]

On Fri, Jun 28, 2024 at 7:46 PM Zhiwei Jiang <jiangzw@tecorigin.com> wrote:
>
> In the original extract32(val, 0, lmul) logic, when lmul is 2 and val is v10 
> or v12,
> there is an issue with this check condition. I think a simple mod operation 
> is sufficient.

Overall looks ok. Do you mind updating the commit message to describe
what exactly this fixes (as in what issue you had) and why this fixes
it

Alistair

>
> Signed-off-by: Zhiwei Jiang <jiangzw@tecorigin.com>
> ---
>  target/riscv/insn_trans/trans_rvv.c.inc | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc 
> b/target/riscv/insn_trans/trans_rvv.c.inc
> index 3a3896ba06..e89b0f2b1e 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -118,7 +118,7 @@ static bool require_nf(int vd, int nf, int lmul)
>   */
>  static bool require_align(const int8_t val, const int8_t lmul)
>  {
> -    return lmul <= 0 || extract32(val, 0, lmul) == 0;
> +    return lmul <= 0 || val % lmul == 0;
>  }
>
>  /*
> --
> 2.17.1
>
>