On 6/25/24 07:46, Alexei Filippov wrote:
Was added call backs for machine specific pmu events.
Simplify monitor functions by adding new hash table, which going to map
counter number and event index.
Was added read/write callbacks which going to simplify support for events,
which expected to have different behavior.
Signed-off-by: Alexei Filippov <alexei.filippov@syntacore.com>
---
Changes since v2:
-rebased to latest master
target/riscv/cpu.h | 9 +++
target/riscv/csr.c | 43 +++++++++-----
target/riscv/pmu.c | 139 ++++++++++++++++++++++-----------------------
target/riscv/pmu.h | 11 ++--
4 files changed, 115 insertions(+), 87 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 6fe0d712b4..fbf82b050b 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -374,6 +374,13 @@ struct CPUArchState {
uint64_t (*rdtime_fn)(void *);
void *rdtime_fn_arg;
+ /*machine specific pmu callback */
+ void (*pmu_ctr_write)(PMUCTRState *counter, uint32_t event_idx,
+ target_ulong val, bool high_half);
+ target_ulong (*pmu_ctr_read)(PMUCTRState *counter, uint32_t event_idx,
+ bool high_half);
+ bool (*pmu_vendor_support)(uint32_t event_idx);
Do these really belong in CPUArchState, rather than RISCVCPUClass?
Surely there's more to this series, since these fields are never set...
r~