Re: [RFC PATCH 06/16] target/riscv: Add hard-coded CPU state of WG extension

[Alistair Francis]

On Wed, Jun 12, 2024 at 6:17 PM Jim Shu <jim.shu@sifive.com> wrote:
>
> Add hard-coded state of WG extension. 'mwid' is the M-mode WID of CPU.
> 'mwidlist' is the list of allowed WID value of 'mlwid' CSR.
>
> These CPU states can be set by CPU option, or can be set by machine code
> via newly added APIs. If we want different WG configs of CPUs, we should
> set it by machine code.
>
> Signed-off-by: Jim Shu <jim.shu@sifive.com>
> ---
>  target/riscv/cpu.c        |  2 ++
>  target/riscv/cpu.h        |  2 ++
>  target/riscv/cpu_cfg.h    |  2 ++
>  target/riscv/cpu_helper.c | 18 ++++++++++++++++++
>  4 files changed, 24 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index d70eedf957..4e87fa4d5b 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -2291,6 +2291,8 @@ static Property riscv_cpu_properties[] = {
>       * it with -x and default to 'false'.
>       */
>      DEFINE_PROP_BOOL("x-misa-w", RISCVCPU, cfg.misa_w, false),
> +    DEFINE_PROP_UINT32("mwid", RISCVCPU, cfg.mwid, UINT32_MAX),
> +    DEFINE_PROP_UINT32("mwidlist", RISCVCPU, cfg.mwidlist, UINT32_MAX),

These should be "x-" as well.

Also same comment about functionality and properties as previous patch

Alistair

>      DEFINE_PROP_END_OF_LIST(),
>  };
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 6fe0d712b4..2d3bfedbba 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -540,6 +540,8 @@ void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, 
> uint32_t priv,
>                                     void *rmw_fn_arg);
>
>  RISCVException smstateen_acc_ok(CPURISCVState *env, int index, uint64_t bit);
> +void riscv_cpu_set_wg_mwid(CPURISCVState *env, uint32_t mwid);
> +void riscv_cpu_set_wg_mwidlist(CPURISCVState *env, uint32_t mwidlist);
>  #endif /* !CONFIG_USER_ONLY */
>
>  void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv);
> diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
> index 23e779ae08..de9c134b15 100644
> --- a/target/riscv/cpu_cfg.h
> +++ b/target/riscv/cpu_cfg.h
> @@ -166,6 +166,8 @@ struct RISCVCPUConfig {
>      bool pmp;
>      bool debug;
>      bool misa_w;
> +    uint32_t mwid;
> +    uint32_t mwidlist;
>
>      bool short_isa_string;
>
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index 161df34626..ff20ab6ab8 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -149,6 +149,24 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
>      *pflags = flags;
>  }
>
> +#ifndef CONFIG_USER_ONLY
> +void riscv_cpu_set_wg_mwid(CPURISCVState *env, uint32_t mwid)
> +{
> +    CPUState *cs = env_cpu(env);
> +    RISCVCPU *cpu = RISCV_CPU(cs);
> +
> +    cpu->cfg.mwid = mwid;
> +}
> +
> +void riscv_cpu_set_wg_mwidlist(CPURISCVState *env, uint32_t mwidlist)
> +{
> +    CPUState *cs = env_cpu(env);
> +    RISCVCPU *cpu = RISCV_CPU(cs);
> +
> +    cpu->cfg.mwidlist = mwidlist;
> +}
> +#endif /* CONFIG_USER_ONLY */
> +
>  void riscv_cpu_update_mask(CPURISCVState *env)
>  {
>      target_ulong mask = 0, base = 0;
> --
> 2.17.1
>
>