Re: [PATCH v8 06/13] target/riscv: Only set INH fields if priv mode is a

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Re: [PATCH v8 06/13] target/riscv: Only set INH fields if priv mode is a

From:	Alistair Francis
Subject:	Re: [PATCH v8 06/13] target/riscv: Only set INH fields if priv mode is available
Date:	Mon, 15 Jul 2024 10:49:00 +1000

On Fri, Jul 12, 2024 at 8:34 AM Atish Patra <atishp@rivosinc.com> wrote:
>
> Currently, the INH fields are set in mhpmevent uncoditionally
> without checking if a particular priv mode is supported or not.
>
> Suggested-by: Alistair Francis <alistair23@gmail.com>
> Signed-off-by: Atish Patra <atishp@rivosinc.com>

Thanks!

Acked-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/csr.c | 29 +++++++++++++++++++++++++----
>  1 file changed, 25 insertions(+), 4 deletions(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index b814d176cbb8..121996edab4b 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -967,13 +967,24 @@ static RISCVException write_mhpmevent(CPURISCVState 
> *env, int csrno,
>  {
>      int evt_index = csrno - CSR_MCOUNTINHIBIT;
>      uint64_t mhpmevt_val = val;
> -
> -    env->mhpmevent_val[evt_index] = val;
> +    uint64_t inh_avail_mask;
>
>      if (riscv_cpu_mxl(env) == MXL_RV32) {
> +        env->mhpmevent_val[evt_index] = val;
>          mhpmevt_val = mhpmevt_val |
>                        ((uint64_t)env->mhpmeventh_val[evt_index] << 32);
> +    } else {
> +        inh_avail_mask = ~MHPMEVENT_FILTER_MASK | MHPMEVENT_BIT_MINH;
> +        inh_avail_mask |= riscv_has_ext(env, RVU) ? MHPMEVENT_BIT_UINH : 0;
> +        inh_avail_mask |= riscv_has_ext(env, RVS) ? MHPMEVENT_BIT_SINH : 0;
> +        inh_avail_mask |= (riscv_has_ext(env, RVH) &&
> +                           riscv_has_ext(env, RVU)) ? MHPMEVENT_BIT_VUINH : 
> 0;
> +        inh_avail_mask |= (riscv_has_ext(env, RVH) &&
> +                           riscv_has_ext(env, RVS)) ? MHPMEVENT_BIT_VSINH : 
> 0;
> +        mhpmevt_val = val & inh_avail_mask;
> +        env->mhpmevent_val[evt_index] = mhpmevt_val;
>      }
> +
>      riscv_pmu_update_event_map(env, mhpmevt_val, evt_index);
>
>      return RISCV_EXCP_NONE;
> @@ -993,11 +1004,21 @@ static RISCVException write_mhpmeventh(CPURISCVState 
> *env, int csrno,
>                                         target_ulong val)
>  {
>      int evt_index = csrno - CSR_MHPMEVENT3H + 3;
> -    uint64_t mhpmevth_val = val;
> +    uint64_t mhpmevth_val;
>      uint64_t mhpmevt_val = env->mhpmevent_val[evt_index];
> +    target_ulong inh_avail_mask = (target_ulong)(~MHPMEVENTH_FILTER_MASK |
> +                                                  MHPMEVENTH_BIT_MINH);
> +
> +    inh_avail_mask |= riscv_has_ext(env, RVU) ? MHPMEVENTH_BIT_UINH : 0;
> +    inh_avail_mask |= riscv_has_ext(env, RVS) ? MHPMEVENTH_BIT_SINH : 0;
> +    inh_avail_mask |= (riscv_has_ext(env, RVH) &&
> +                       riscv_has_ext(env, RVU)) ? MHPMEVENTH_BIT_VUINH : 0;
> +    inh_avail_mask |= (riscv_has_ext(env, RVH) &&
> +                       riscv_has_ext(env, RVS)) ? MHPMEVENTH_BIT_VSINH : 0;
>
> +    mhpmevth_val = val & inh_avail_mask;
>      mhpmevt_val = mhpmevt_val | (mhpmevth_val << 32);
> -    env->mhpmeventh_val[evt_index] = val;
> +    env->mhpmeventh_val[evt_index] = mhpmevth_val;
>
>      riscv_pmu_update_event_map(env, mhpmevt_val, evt_index);
>
>
> --
> 2.34.1
>
>

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[PATCH v8 00/13] Add RISC-V ISA extension smcntrpmf support, Atish Patra, 2024/07/11
- [PATCH v8 01/13] target/riscv: Combine set_mode and set_virt functions., Atish Patra, 2024/07/11
- [PATCH v8 04/13] target/riscv: Add cycle & instret privilege mode filtering definitions, Atish Patra, 2024/07/11
- [PATCH v8 03/13] target/riscv: Add cycle & instret privilege mode filtering properties, Atish Patra, 2024/07/11
  - Re: [PATCH v8 03/13] target/riscv: Add cycle & instret privilege mode filtering properties, Alistair Francis, 2024/07/14
- [PATCH v8 02/13] target/riscv: Fix the predicate functions for mhpmeventhX CSRs, Atish Patra, 2024/07/11
- [PATCH v8 06/13] target/riscv: Only set INH fields if priv mode is available, Atish Patra, 2024/07/11
  - Re: [PATCH v8 06/13] target/riscv: Only set INH fields if priv mode is available, Alistair Francis <=
- [PATCH v8 07/13] target/riscv: Implement privilege mode filtering for cycle/instret, Atish Patra, 2024/07/11
- [PATCH v8 05/13] target/riscv: Add cycle & instret privilege mode filtering support, Atish Patra, 2024/07/11
  - Re: [PATCH v8 05/13] target/riscv: Add cycle & instret privilege mode filtering support, Alistair Francis, 2024/07/14
- [PATCH v8 08/13] target/riscv: Save counter values during countinhibit update, Atish Patra, 2024/07/11
- [PATCH v8 09/13] target/riscv: Enforce WARL behavior for scounteren/hcounteren, Atish Patra, 2024/07/11
- [PATCH v8 12/13] target/riscv: Do not setup pmu timer if OF is disabled, Atish Patra, 2024/07/11
- [PATCH v8 11/13] target/riscv: More accurately model priv mode filtering., Atish Patra, 2024/07/11
- [PATCH v8 13/13] target/riscv: Expose the Smcntrpmf config, Atish Patra, 2024/07/11
  - Re: [PATCH v8 13/13] target/riscv: Expose the Smcntrpmf config, Alistair Francis, 2024/07/14
- [PATCH v8 10/13] target/riscv: Start counters from both mhpmcounter and mcountinhibit, Atish Patra, 2024/07/11

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